MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 560

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
30-10
DRc[4:0]
Reset
Reset
31–28
23–20
19–17
Bits
27
26
25
24
16
15
14
W
W
R
R MAP TRC EMU
31
15
0
0
BSTAT
Name
BKPT
HALT
MAP
TRG
HRL
TRC
FOF
IPW
30
14
0
0
—
BSTAT
Figure 30-7. Configuration/Status Register (CSR)
29
13
0
0
Breakpoint status. Provides read-only status information concerning hardware
breakpoints. BSTAT is cleared by a TDR write or by a CSR read when either a level-2
breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is
disabled.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM. FOF
is cleared whenever CSR is read.
Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor
core and forced entry into BDM. Reset, the debug
TRG.
Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM.
Reset, the debug
Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM.
Reset, the debug
Hardware revision level. Indicates the level of debug module functionality. An emulator
could use this information to identify the level of functionality supported.
0000 Initial debug functionality (Revision A) (This is the only valid value for the MCF5271)
Reserved, should be cleared.
Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug
module’s programming model registers. IPW can be modified only by commands from the
external development system.
Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space,
Force emulation mode on trace exception. If TRC = 1, the processor enters emulator
mode when a trace exception occurs. If TRC=0, the processor enters supervisor mode.
TT = 10, TM = 101 or 110.
28
12
0
0
DDC
Table 30-9. CSR Field Descriptions
FOF TRG HALT BKPT
27
11
0
0
MCF5271 Reference Manual, Rev. 2
UHE
26
10
0
0
GO
GO
command, or reading CSR will clear HALT.
command, or reading CSR will clear BKPT.
25
0
0
9
BTB
24
0
0
8
0x00
Description
23
0
0
0
7
NPL
22
0
6
0
HRL
GO
IPI
21
0
0
5
command, or reading CSR will clear
SSM
20
0
0
4
19
0
0
0
0
3
Freescale Semiconductor
18
0
0
0
0
2
17
0
0
0
0
1
IPW
16
0
0
0
0