MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 175

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

8.3.2.21 JTAG
The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not
affected by the system clock. The JTAG cannot generate an event to cause the CPU to exit any
low-power mode. Toggling TCLK during any low-power mode will increase the system current
consumption.
8.3.3
The functionality of each of the peripherals and CPU during the various low-power modes is
summarized in
the peripheral automatically assumes when the STOP instruction is executed and the
LPCR[LPMD] field is set for the particular low-power mode. Individual peripherals may be
disabled by programming its dedicated control bits. The wakeup capability field refers to the
ability of an interrupt or reset by that peripheral to force the CPU into run mode.
Freescale Semiconductor
CPU
SRAM
System Control Module
SDRAM Controller
Chip Select Module
DMA Controller
UART0, UART1 and UART2
I
QSPI
DMA Timers
Interrupt controller
Fast Ethernet Controller
I/O Ports
Reset Controller
Chip Configuration Module
Power Management
Clock Module
Edge port
Watchdog timer
2
C Module
Summary of Peripheral State During Low-Power Modes
Table
Module
Table 8-5. CPU and Peripherals in Low-Power Modes
8-5. The status of each peripheral during a given mode refers to the condition
MCF5271 Reference Manual, Rev. 2
Program
Stopped
Stopped
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Wait Mode
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Peripheral Status
No
No
No
No
No
No
No
2
2
2
2
2
2
3
2
2
3
3
Program
Stopped
Stopped
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Doze Mode
1
/ Wakeup Capability
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
2
2
2
2
2
2
3
2
2
3
3
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Enabled
Stopped
Enabled
Enabled
Stopped
Stopped
Enabled
Stopped
Stopped
Functional Description
Stop Mode
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
2
3
2
2
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