MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 381

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

The 7-wire serial mode interface (RCR[MII_MODE] = 0) operates in what is generally referred
to as the “AMD” mode. 7-wire mode connections to the external transceiver are shown in
Table
19.3.6 FEC Frame Transmission
The Ethernet transmitter is designed to work with almost no intervention from software. Once
ECR[ETHER_EN] is asserted and data appears in the transmit FIFO, the Ethernet MAC is able to
transmit onto the network.
When the transmit FIFO fills to the watermark (defined by the TFWR), the MAC transmit logic
will assert ETXEN and start transmitting the preamble (PA) sequence, the start frame delimiter
(SFD), and then the frame information from the FIFO. However, the controller defers the
transmission if the network is busy (ECRS asserts). Before transmitting, the controller waits for
carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit times. If
so, the transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense
originally became inactive). See
Freescale Semiconductor
19-35.
Table 19-35. 7-Wire Mode Configuration
SIGNAL DESCRIPTION
Management Data Clock
Receive Data Valid
Table 19-34. MII Mode (Continued)
Signal Description
Receive Data Valid
Transmit Enable
Management Data
Transmit Clock
Receive Clock
Transmit Data
Receive Data
Receive Error
Section 19.3.14.1, “ Transmission
Receive Data
Input/Output
Collision
MCF5271 Reference Manual, Rev. 2
EMAC pin
ERXD[3:0]
EMAC PIN
ERXDV
ERXER
EMDIO
EMDC
ERXCLK
ETXCLK
ERXD[0]
ETXD[0]
ERXDV
ETXEN
ECOL
Errors” for more details.
Functional Description
19-37