MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 10

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
6.3.1.4
6.3.1.5
6.3.2
6.3.2.1
6.3.2.2
6.3.2.3
6.3.2.4
6.3.2.5
6.3.2.6
6.4
6.4.1
6.4.2
7.1
7.1.1
7.1.2
7.1.2.1
7.1.2.2
7.1.3
7.1.3.1
7.1.3.2
7.1.3.3
7.1.3.4
7.1.4
7.1.5
7.1.5.1
7.1.5.2
7.1.6
7.1.7
7.1.7.1
7.1.7.2
7.1.7.3
7.1.7.4
7.1.7.5
7.2
7.3
7.3.1
7.3.1.1
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MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Initialization/Applications Information ......................................................................... 6-16
Overview.......................................................................................................................... 7-1
PowerPC Architecture Implementation ......................................................................... 7-13
Implementation-Specific Information............................................................................ 7-13
Bus Error Detection ................................................................................................... 6-13
Initialization Sequence............................................................................................... 6-16
Error Handling Sequence........................................................................................... 6-16
Features........................................................................................................................ 7-3
Instruction Unit ............................................................................................................ 7-6
Independent Execution Units....................................................................................... 7-7
Completion Unit .......................................................................................................... 7-8
Memory Subsystem Support........................................................................................ 7-8
Bus Interface Unit (BIU) ........................................................................................... 7-10
System Support Functions ......................................................................................... 7-11
Register Model........................................................................................................... 7-14
Address Bus Parking.............................................................................................. 6-13
Data Bus Arbitration.............................................................................................. 6-13
Address Time Out .................................................................................................. 6-13
Data Time Out ....................................................................................................... 6-14
Transfer Error ........................................................................................................ 6-14
Address Only Transaction Type............................................................................. 6-14
Reserved Transaction Type.................................................................................... 6-15
Illegal (eciwx/ecowx) Transaction Type................................................................ 6-15
Instruction Queue and Dispatch Unit ...................................................................... 7-6
Branch Processing Unit (BPU)................................................................................ 7-7
Integer Unit (IU) ...................................................................................................... 7-7
Floating-Point Unit (FPU) ....................................................................................... 7-7
Load/Store Unit (LSU) ............................................................................................ 7-8
System Register Unit (SRU).................................................................................... 7-8
Memory Management Units (MMUs)..................................................................... 7-9
Cache Units............................................................................................................ 7-10
Power Management ............................................................................................... 7-11
Time Base/Decrementer ........................................................................................ 7-11
JTAG Test and Debug Interface............................................................................. 7-12
Core Performance Monitor .................................................................................... 7-12
UISA Registers ...................................................................................................... 7-16
Clock Multiplier.................................................................................................... 7-12
e300 Processor Core Overview
Contents
Chapter 7
Title
Freescale Semiconductor
Number
Page