MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 851

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-135
15.5.4.3.10 TBI Control Register (TBICON)
Figure 15-126
Offset 0x11
Freescale Semiconductor
Reset
6–15
Bits
1–3
4–5
0
W
R
Soft_Reset
Custom Jitter
Jitter Enable Jitter enable. This bit is cleared by default.
Jitter Select
0
0
Pattern
Name
—
describes the fields of the JD register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
describes the definition for the TBICON register.
—
0
1
0 Normal transmit operation.
1 Enable the TBI to transmit the jitter test patterns defined in IEEE 802.3z 36A.
Selects the jitter pattern to be transmitted in diagnostics mode. Encoding of this field is shown in the
following table. Default is 00.
Reserved
Used in conjunction with jitter (pattern) select and jitter (diagnostic) enable; set this field to the desired
custom pattern which is continuously transmitted. Its default is 0x000.
User defined uses custom jitter pattern, bits 6–15
High frequency (+/- D21.5)
1010101010101010101010101010101010101010…
Mixed frequency (+/- K28.5)
1111101011000001010011111010110000010100…
Low frequency
1111100000111110000011111000001111100000…
Complex pattern (10’h17c,10’h0c9,10’h0e5,10’h2a3, 10’h17c,...)
Square Wave (- K28.7)
0011111000001111100000111110000011111000…
Reserved
Reserved
Disable
Rx Dis
0
2
Disable
Tx Dis
Figure 15-126. TBI Control Register Definition
0
3
Table 15-135. JD Field Descriptions
0
4
Jitter Pattern Select
—
0
0
6
Sense
AN
7
0
Description
0
8
—
0
9
Enhanced Three-Speed Ethernet Controllers
Select
Clock
10
0
bit[1]
Mode
0
0
0
0
1
1
1
1
MII
11
1
bit[2]
0
0
1
1
0
0
1
1
12
0
bit[3]
13
0
0
1
0
1
0
1
0
1
Access: Mixed
—
14
0
15-133
15
0