MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1112

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DUART
18.3
There are two complete sets of DUART registers (one for UART1 and one for UART2). The two UARTs
are identical, except that the registers for UART1 are located at offsets 0x0_4500 (local), and the registers
for UART2 are located at offsets 0x0_4600 (local). Throughout this chapter, the registers are described by
a singular acronym: for example, LCR represents the line control register for either UART1 or UART2.
The registers in each UART interface are used for configuration, control, and status. The divisor latch
access bit, ULCR[DLAB], is used to access the divisor latch least- and most-significant bit registers and
the alternate function register. Refer to
for more information on ULCR[DLAB].
All DUART registers are one byte wide; reads and writes to these registers must be byte-wide operations.
Table 18-3
information about each register. Undefined byte address spaces within offset 0x4000–0x4FFF are
reserved.
18-4
DSP_UART_SOUT
UART_SOUT[1:2]/
0x0_4500
UART_CTS[1:2]
UART_RTS[1:2]
Offset
Signal
Memory Map/Register Definition
provides a register summary with references to the section and page that contain detailed
URBR—ULCR[DLAB] = 0 UART1 receiver buffer register
UTHR—ULCR[DLAB] = 0 UART1 transmitter holding register
UDLB—ULCR[DLAB] = 1 UART1 divisor least significant byte register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 18-2. DUART Signals—Detailed Signal Descriptions (continued)
I/O
O
O
I
Serial data out. The serial data output signals for the UART1, UART2, or DSP_UART are set (mark
condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is
shifted out on these signals, with the least significant bit transmitted first.
Clear to send. Connected to the respective RTS outputs of the other UART devices on the bus. They
can be programmed to generate an interrupt on change-of-state of the signal.
Request to send. Can be programmed to be automatically negated and asserted by either the
receiver or transmitter. When connected to the CTS input of a transmitter, this signal can be used to
control serial data flow.
Meaning
Meaning
Meaning
Timing Assertion/Negation—An internal logic sample signal, rxcnt , uses the frequency of the
Timing Assertion/Negation—Sampled at the rising edge of every system clock.
Timing Assertion/Negation—Updated and driven at the rising edge of every system clock.
State
State
State
Asserted/Negated—Represents the data transmitted on the respective UART interface.
Asserted/Negated—Represent the clear to send condition for their respective UART.
Asserted/Negated—Represents the data being transmitted on the respective UART
Table 18-3. DUART Register Summary
baud-rate generator to update and drive the data on SOUT.
interface.
Section 18.3.1.7, “Line Control Registers (ULCR1 and ULCR2),”
Register
Description
Access Reset
R/W
W
R
0x00
0x00
0x00
Freescale Semiconductor
Section/Page
18.3.1.1/18-5
18.3.1.2/18-6
18.3.1.3/18-6