MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 476

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x0_50B8
Reset
Reset
Enhanced Local Bus Controller
10.3.1.11 Transfer Error Interrupt Enable Register (LTEIR)
The transfer error interrupt enable register (LTEIR), shown in
error/event reporting through the eLBC internal interrupt mechanism. Software should clear pending
errors/events in LTESR before enabling interrupts. After an interrupt has occurred, clearing relevant
LTESR error/event bits negates the interrupt.
Table 10-18
10-28
13–29
Bits
Bits
3–4
30
31
W
W
0
1
2
R
R
BMI
16
0
UCCD UPM Run pattern command completion checking disable.
Name
Name
CCD
FCTI
PARI
BMI
—
—
FCTI PARI
describes LTEIR fields.
1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
0 UPM Run pattern command completion checking is enabled.
1 UPM Run pattern command completion checking is disabled.
FCM command completion checking disable.
0 Command completion checking is enabled.
1 Command completion checking is disabled.
Bus monitor error interrupt enable.
0 Bus monitor error reporting is disabled.
1 Bus monitor error reporting is enabled.
FCM command time-out interrupt enable.
0 FCM command time-out error reporting is disabled.
1 FCM command time-out error reporting is enabled.
ECC error interrupt enable.
0 ECC error reporting is disabled.
1 ECC error reporting is enabled.
Reserved
2
Figure 10-15. Transfer Error Interrupt Enable Register (LTEIR)
3
Table 10-17. LTEDR Field Descriptions (continued)
—
4
Table 10-18. LTEIR Field Descriptions
WPI
5
6
—
—
7
All zeros
All zeros
WARA RAWA
Description
Description
8
Figure
9
10
10-15, is used to send or block
—
11
CSI
12
Freescale Semiconductor
13
29
Access: Read/Write
UCCI
—
30
CCI
15
31