MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1161

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

3.1, 3-9
Chapter 4
4.1.1, 4-1
4.3.2.2, 4-14
4.3.2.2.4, 4-17
4.3.2.2.4, 4-17
4.3.3.1.1, 4-23
4.4.4, 4-32
4.4.7, 4-32
4.5.1, 4-33
4.5.1.6, 4-37
Freescale Semiconductor
LB_POR_CFG_BOOT
_ECC_DIS
RCWHR
9–11
Bits
ROMLOC
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Field
Boot time ECC
checking
(Binary)
Value
In Table 3-1, added the following row after LCLK[0:1]:
Throughout chapter—Editing done for consistency.
In Table 4-1, in the Description column for SRESET, changed the Timing,
Negation statement to read: ‘Occurs after being serviced.’
In Table 4-11, in the Description column for bits 9–11, added a sentence after the
first sentence as follows:
This bit combined with bit RLEXT determines where the device boots from.
Second paragraph, first sentence, was changed to read as follows:
The boot ROM location reset configuration word field, shown in Table 4-5,
establishes the location of boot ROM.
Combined Table 4-15 and Table 4-16, creating a new Table 4-15 as follows:
Deleted Table 4-16 and renumbered the rest of the tables in the chapter.
In Table 4-23, in the NOR Flash row, changed the setting for BR0[PS] to 10.
Second paragraph, last sentence, changed to read as follows:
When using the single crystal option, the frequency for SYS_CLK_IN must be
chosen such that the USB reference will be 24 or 48 MHz when utilizing the
divide by 1 or 2 option, that is, the SYS_CLK_IN must be 24 or 48 MHz.
Removed Section 4.4.7, “Clock Summary,” and Table 4-28. Renumbered the rest
of the tables in the chapter.
In Table 4-29, added a ‘Reset’ column.
In Table 4-33, bit 31, changed the description to read as follows:
Reserved, this bit should never be set.
000
001
010
011
100
101
110
111
DDR SDRAM
PCI
Reserved, should be cleared
Reserved, should be cleared
Reserved
Local bus GPCM—8-bit ROM
Local bus GPCM—16-bit ROM
Reserved
Legacy Mode (RLEXT = 00)
Table 4-15. Boot ROM Location
eLBC
1
1
Meaning
Local bus NAND Flash—8-bit large page ROM
Reserved
Reserved
Local bus NAND Flash—8-bit small page ROM
Reserved
Reserved
Reserved
Reserved
—
NAND Flash Mode (RLEXT = 01)
TSEC_MDC
Revision History
A-3