MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 887

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.6.4.2.2
By default, extracted properties are compared arithmetically according to the CMP field in each RQCTRL
word. This permits point value matches in each table entry, and range checks across a pair of table entries
combined with the AND attribute in RQCTRL. However, inspection of the parse flags, Ethernet preamble,
and IP addresses typically requires “don’t care” bit fields in the properties to be cleared as part of the
comparison. The eTSEC provides a dedicated 32-bit register, known as the mask_register, for performing
such masking operations. At the start of each table search by the filer, mask_register is reset to
0xFFFF_FFFF, which ensures that no masking occurs.
Filer rules may be configured to assign specific bit patterns to mask_register. Such rules can be configured
to either match always (useful for implementing a default rule and specifying an associated receive queue),
or fail always (which prevents termination of the filer table search). Once mask_register has been assigned,
it retains its value until it is reassigned or the table search terminates. All properties are non-destructively
bit-wise ANDed with mask_register prior to comparison in subsequent rules, which allows an entire
cluster of rules to make use of a common mask. Individual masks for specific rules can also be created
simply by combining a mask_register assignment (match always form) with a regular rule using the AND
attribute.
To create a mask_register assignment rule, it is necessary to select PID = 0 in RQCTRL, and choose CMP
such that the rule either matches (CMP = 01) or fails (CMP = 11). In this entry, RQPROP is then considered
to be the assigned bit vector.
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The AND field in RQCTRL allows more than one comparison in a sequence to be chained together
as a Boolean AND condition. Setting AND = 1 defers evaluation of the rule until the next entry has
been matched, which may, in turn, have AND set. If any comparison involving AND = 1 fails, the
entire chained sequence fails. A typical use for AND is to combine a pair of comparisons in a range
match; the first such entry has AND = 1, the second has AND = 0 and its values of Q and REJ take
effect.
The CLE field in RQCTRL offers a way to bracket a set of consecutive—perhaps related—rules
into a rule cluster. A cluster must be preceded by a guard rule, which simply determines whether
the cluster rules can be evaluated. If the guard rule succeeds and its last entry has both CLE = 1 and
AND = 1, the cluster rules that follow are enabled. The cluster ends at the first entry where CLE =
1 and AND = 0, which may also belong to a rule that files or rejects a frame. If the guard rule fails,
all rules in the cluster are skipped, including mask_register assignments. Clusters must not be
nested.
The GPI field offers the user the ability to interrupt the core upon matching a rule that causes a
frame to be filed to memory. Once the last RxBD corresponding to that frame is written to memory,
the IEVENT[FGPI] event will be asserted. This bit will be set regardless of any interrupt
coalescing that may be set.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Comparing Properties with Bit Masks
Enhanced Three-Speed Ethernet Controllers
15-169