MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 926

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15-208
Set up the MII Mgmt for a read cycle to TBI’s Control register (write the PHY address and Register address),
Initialize SerDes to select SGMII. The initialization sequence should be prepended with SerDes initialization.
Set up the MII Mgmt for a write cycle to TBICON register (write the PHY address and Register address),
set source clock divide by 14 for example to insure that MDC clock speed is not greater than 2.5 MHz
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
This sets TBI in single clock mode and MII Mode off to enable communication with SerDes.
Perform an MII Mgmt read cycle to verify state of TBI Control Register (optional)
(Uses the TBI address and Register address placed in MIIMADD register),
Writing to MII Mgmt Control with 16-bit data intended for TBICON register,
the control register (CR) is at offset address 0x00 from the TBI’s address.
The TBICON register is at offset address 0x11 from the TBI’s address.
read the MIIMSTAT and look for AN Enable and other bit information.
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
Table 15-178. SGMII Mode Register Initialization Steps
(This example has Statistics Enable = 1, TBIM = 1, SGMIIM = 1)
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
MIIMCON[0000_0000_0000_0000_0000_0000_0010_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0001_0001]
ECNTRL[0000_0000_0000_0000_0001_0000_0010_0010]
MIIMCFG[0000_0000_0000_0000_000_0000_0000_0101]
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
(Set I/F mode = 1 in SGMII 10/100 Mbps speed)
(Set R100M = 1 in SGMII 100 Mbps speed)
Perform an MII Mgmt write cycle to TBI.
Assign a Physical address to the TBI,
Setup the MII Mgmt clock speed,
to 02608C:876543, for example.
to 02608C:876543, for example.
(I/F Mode = 2, Full Duplex = 1)
Initialize MAC Station Address
Initialize MAC Station Address
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
set to 16, for example.
Initialize MACCFG2,
Initialize ECNTRL,
Clear Soft_Reset,
Set Soft_Reset,
Freescale Semiconductor