MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1056

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.8
The function of the device operation is to transfer a request in the memory image to and from the Universal
Serial Bus. Using a set of linked list transfer descriptors, pointed to by a queue head, the device controller
will perform the data transfers. The following sections explain the use of the device controller from the
device controller driver (DCD) point-of-view and further describe how specific USB bus events relate to
status changes in the device controller programmer's interface.
16.8.1
After hardware reset, the USB DR module is disabled until the run/stop bit (USBCMD[RS]) is set to a '1'.
In the disabled state, the pull-up on the USB D+ is not active which prevents an attach event from
occurring. At a minimum, it is necessary to have the queue heads setup for endpoint zero before the device
attach occurs. Shortly after the device is enabled, a USB reset will occur followed by setup packet arriving
at endpoint 0. A queue head must be prepared so that the device controller can store the incoming setup
packet.
The MPC8313E USB PHY and clock must be configured prior to initialization of the USB controller.
Initialization of the MPC8313E USB PHY interface is performed via software control following a
power-on reset.
In order to initialize a device, the software should perform the following steps:
16-128
31–12 Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will typically set
31–12 Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will typically set
10–0
11–0
Bits
Bits
11
1. Set the controller mode to device mode. Optionally set USBMODE[SDIS] (streaming disable).
2. Optionally modify the BURSTSIZE register.
3. Program PORTSC[PTS] if using a non-ULPI PHY.
the buffer pointers to a series of incrementing integers.
Reserved
Frame Number. Written by the device controller to indicate the frame number in which a packet finishes. This is typically
be used to correlate relative completion times of packets on an ISO endpoint.
the buffer pointers to a series of incrementing integers.
Reserved
Device Operational Model
Device Controller Initialization
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Transitioning from host mode to device mode requires a device controller
reset before modifying USBMODE.
Table 16-82. Buffer Pointer Pages 2–4
Table 16-81. Buffer Pointer Page 1
NOTE
Description
Description
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