MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1095

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

17.4.1.1
When the I
transfer by sending a START condition. As shown in
high-to-low transition of SDAn while SCLn is high. This condition denotes the beginning of a new data
transfer. Each data transfer can contain several bytes and awakens all slaves. The START condition is
initiated by a software write that sets I2CnCR[MSTA].
17.4.1.2
The first byte of data transferred by the master immediately after the START condition is the slave address.
This is a seven-bit calling address followed by a R/W bit, which indicates the direction of the data
transferred to the slave. Each slave in the system has a unique address. When the I
as a master, it must not transmit an address that is the same as its slave address. An I
master and slave at the same time.
Only the slave with a calling address that matches the one transmitted by the master responds by returning
an acknowledge bit (negating the SDAn signal at the 9th clock) as shown in
acknowledges the address, the master should generate a STOP condition or a repeated START condition.
When slave addressing is successful (and SCLn returns to zero), the data transfer can proceed on a
byte-to-byte basis in the direction specified by the R/W bit sent by the calling master.
The I
address is always zero; however the I
broadcast message is the master address. Because the second byte is automatically acknowledged by
hardware, the receiver device software must verify that the broadcast message is intended for itself by
reading the second byte of the message. If the master address is for another receiver device and the third
byte is a write command, software can ignore the third byte during the broadcast. If the master address is
for another receiver device and the third byte is a read command, software must write 0xFF to I2CnDR
with I2CnCR[TXAK] = 1, so that it does not interfere with the data written from the addressed device.
Each data byte is 8 bits long. Data bits can be changed only while SCLn is low and must be held stable
while SCLn is high, as shown in
most significant bit (msb) is transmitted first. Each byte of data must be followed by an acknowledge bit,
which is signaled from the receiving device by pulling SDAn low at the 9th clock. Therefore, one complete
data byte transfer takes 9 clock pulses. Several bytes can be transferred during a data transfer session.
If the slave receiver does not acknowledge the master, the SDAn line must be left high by the slave. The
master can then generate a stop condition to abort the data transfer or a START condition (repeated
START) to begin a new calling.
If the master receiver does not acknowledge the slave transmitter after a byte of transmission, the slave
interprets that the end-of-data has been reached. Then the slave releases the SDAn line for the master to
generate a STOP or a START condition.
Freescale Semiconductor
2
C module responds to a general call (broadcast) command when I2CnCR[BCST] is set. A broadcast
2
C bus is not engaged (both SDAn and SCLn lines are at logic high), a master can initiate a
START Condition
Slave Address Transmission
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure
2
C module does not check the R/W bit. The second byte of the
17-8. There is one clock pulse on SCLn for each data bit, and the
Figure
17-8, a START condition is defined as a
Figure
2
C module is operating
17-8. If no slave
2
C device cannot be
I
2
C Interfaces
17-11