MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 903

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.6.7
The eTSEC buffer descriptor (BD) is modeled after the MPC8260 Fast Ethernet controller BD for ease of
reuse across the PowerQUICC network processor family. Drawing from the MPC8260 FEC BD
programming model, the eTSEC descriptor base registers point to the beginning of BD rings. The eTSEC
BD also expands upon the MPC8260 BD model to accommodate the eTSEC’s unique features. However,
the 8-byte data BD format is designed to be compatible with the existing MPC8260 BD model.
15.6.7.1
Data buffers are used in the transmission and reception of Ethernet frames (see
encapsulate all information necessary for the eTSEC to transmit or receive an Ethernet frame. Within each
data BD there is a status field, a data length field, and a data pointer. The BD completely describes an
Ethernet packet by centralizing status information for the data packet in the status field of the BD and by
containing a data BD pointer to the location of the data buffer. Software is responsible for setting up the
BDs in memory. Because of pre-fetching, a minimum of four buffer descriptors per ring are required. This
applies to both the transmit and the receive descriptor rings. Transmit rings are limited to a maximum size
of 65536 BDs due to BD and frame data prefetching. Software also must have the data pointer pointing to
a legal memory location. Within the status field, there exists an ownership bit which defines the current
state of the buffer (pointed to by the data pointer). Other bits in the status field of the buffer descriptor are
used to communicate status/control information between the eTSEC and the software driver.
Because there is no next BD pointer in the transmit/receive BD (see
sequentially in memory. The eTSEC increments the current BD location appropriately to the next BD
location to be processed. There is a wrap bit in the last BD that informs the eTSEC to loop back to the
beginning of the BD chain. Software must initialize the TBASE and RBASE registers that point to the
beginning transmit and receive BDs for eTSEC.
Freescale Semiconductor
Bytes
4–5
6–7
0–15
0–15
Bits
Buffer Descriptors
Data Buffer Descriptors
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
VLCTL/
PTP_ID
Name
PHCS
Table 15-162. Tx Frame Control Block Description (continued)
Pseudo-header checksum (16-bit one’s complement sum with carry wraparound, but without
result inversion) for TCP or UDP packets, calculated by software. Valid only if NPH = 1.
VLAN control word for insertion in the transmitted VLAN tag. Valid only if VLN = 1.Tx PTP
packet identification number. This number will be copied into the Tx PTP packet timestamp
identification field. PTP field takes precedence over VLN field.
Description
Figure
Enhanced Three-Speed Ethernet Controllers
15-145), all BDs must reside
Figure
15-144). Data BDs
15-185