MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1180

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
operations will not be able execute. Undefined behavior results if a read or write operation is performed
when ULPISS is cleared. To execute a wakeup operation, write all 32-bits of the ULPI Viewport where
ULPIPORT is constructed appropriately and the ULPIWU bit is set and the ULPIRUN bit is cleared. Poll
the ULPI Viewport until ULPIWU is cleared for the operation to complete.
To execute a read or write operation, write all 32-bits of the ULPI Viewport where ULPIDATWR,
ULPIADDR, ULPIPORT, ULPIRW are constructed appropriately and the ULPIRUN bit is set. Poll the
ULPI Viewport until ULPIRUN is cleared for the operation to complete. For read operations,
ULPIDATRD is valid once ULPIRUN is cleared.
The polling method above can be replaced with interrupts using the ULPI interrupt defined in the USBSTS
and USBINTR registers. When a wakeup or read/write operation completes, the ULPI interrupt is set.
16.3.2.13, 16-25
16.3.2.15, 16-31
16.3.2.24, 16-38
16.3.2.26, 16-40
A-22
23
31
PHCD PHY low power suspend. This bit is not defined in the EHCI specification.
rd_prefetch_val Selects whether 32 bytes or 64 bytes are fetched during burst read transactions at the system
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Host mode:
Device mode:
0 Normal PHY operation.
1 Signal the PHY to enter low power suspend mode
Reading this bit indicates the status of the PHY.
Note: If there is no clock connected to the USBDR_CLK signals, PHCD must be set and the following
registers should not be written: DEVICE_ADDR/PERIODICLISTBASE, PORTSC, ENDPTCTRL0,
ENDPTCTRL1, ENDPTCTRL2.
• The PHY can be put into low power suspend —when the downstream device has been put into suspend
• The PHY can be put into low power suspend—when the device is not running (USBCMD[RS] = 0b) or
mode or when no downstream device is connected. Low power suspend is completely under the control of
software.
suspend signaling is detected on the USB. Low power suspend will be cleared automatically when the
resume signaling has been detected or when forcing port resume.
interface. When this input is LOW 64 bytes are fetched and when it is HIGH 32 bytes are fetched.
The setting of rd_prefetch_val must match the setting of the larger of TXPBURST and RXPBURST
fields in the BURSTSIZE register. If either of these fields is 64 bytes, then rd_prefetch_val must be
left cleared. Otherwise, this value should be set.
0 64-byte fetch
1 32-byte fetch
In Table 16-22, changed the description for bit 23 with the following:
In Table 16-24, “OTGSC Register Field Descriptions,” corrected bit field
description of field 7–5 from “Reserved, should be cleared” to “Reserved, writes
should preserve reset value.”
In fourth paragraph, second sentence, changed as follows:
If AGE_CNT_THRESH is equal to zero, priority state one is always chosen.
In Table 16-35, bit 31, changed the description to read as follows:
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