MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 202

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MPC8313CZQADDC

Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8313CZQADDC

Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4

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Part Number:
MPC8313CZQADDC
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Reset, Clocking, and Initialization
Table 4-30
4.5.1.6
RCR, shown in
writing to this register, the user must enable it by writing the value 0x5253_5445 to the RPR.
Table 4-31
4-36
Address 0x0_091C
0–31
0–29
Bits
Bits
Reset
Reset
30
31
W
W
R
R
RCPW Reset control protection word. Prevents unintended software reset requests because of a write to the RCR.
SWHR Software hard reset. Setting this bit causes the device to begin a hard reset flow. This bit returns to its reset
Name
Name
16
0
defines the bit fields of RPR.
defines the bit fields of RCR.
Reset Control Register (RCR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The user should write the value 0x5253_5445 (RSTE in ASCII) to enable. Enable indication appears in the
reset control enable register (RCER[CRE]). Reading this register always returns all zeros.
Reserved, should be cleared.
state during the reset sequence, so reading it always returns all zeros.
Reserved. This bit should never be set.
Figure
4-11, can be used by software to initiate a soft or hard reset sequence. To allow
Figure 4-11. Reset Control Register (RCR)
Table 4-30. RPR Bit Descriptions
Table 4-31. RCR Bit Settings
All zeros
All zeros
Description
Description
Freescale Semiconductor
Access: User read/write
29
SWHR
30
15
31

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