MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1098

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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17.4.2.1
The arbitration control block controls the arbitration procedure of the master mode. A loss of arbitration
occurs whenever the master detects a 0 on the external SDAn line while attempting to drive a 1, tries to
generate a START or repeated START at an inappropriate time, or detects an unexpected STOP request on
the line.
In master mode, arbitration by the master is lost (and I2CnSR[MAL] is set) under the following conditions:
Note that the I
17.4.3
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices can hold
SCLn low after completion of a 1-byte transfer (9 bits). In such cases, it halts the bus clock and forces the
master clock into wait states until the slave releases the SCLn line.
17.4.4
The clock control block handles requests from the clock signal for transferring and controlling data for
multiple tasks.
A 9-cycle data transfer clock is requested for the following conditions:
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C Interfaces
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Master mode—the I
is initiated, the current bus cycle can be corrupted. This ultimately causes in the current bus master
to lose arbitration, after which bus operations return to normal.
SDAn samples low when the master drives high during an address or data-transmit cycle
(transmit).
SDAn samples low when the master drives high during a data-receive cycle of the acknowledge
(ACK) bit (receive).
A START condition is attempted when the bus is busy.
A repeated START condition is requested in slave mode.
A repeated START condition is attempted when the requesting device is not the bus owner
Unexpected STOP condition detected
Master mode
— Transmit slave address after START condition
— Transmit slave address after repeated START condition
— Transmit data
— Receive data
Slave mode
— Transmit data
— Receive data
— Receive slave address after START or repeated START condition
Handshaking
Clock Control
Arbitration Control
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C module does not automatically retry a failed transfer attempt.
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C module cannot tell whether the bus is busy; therefore, if a START condition
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