MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 28

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
15.6.3.1
15.6.3.2
15.6.3.3
15.6.4
15.6.4.1
15.6.4.2
15.6.4.2.1
15.6.4.2.2
15.6.4.2.3
15.6.4.2.4
15.6.4.2.5
15.6.4.2.6
15.6.4.2.7
15.6.4.2.8
15.6.4.3
15.6.4.3.1
15.6.4.3.2
15.6.5
15.6.5.1
15.6.5.2
15.6.5.2.1
15.6.5.2.2
15.6.6
15.6.6.1
15.6.6.2
15.6.6.3
15.6.6.3.1
15.6.6.4
15.6.6.4.1
15.6.6.5
15.6.6.5.1
15.6.6.5.2
15.6.6.6
15.6.7
15.6.7.1
15.6.7.2
15.6.7.3
15.7
15.7.1
15.7.1.1
15.7.1.2
xxviii
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Initialization/Application Information ....................................................................... 15-192
Quality of Service (QoS) Provision ....................................................................... 15-165
Lossless Flow Control ........................................................................................... 15-175
Hardware Assist for IEEE Std. 1588-CompatibleTimestamping .......................... 15-178
Buffer Descriptors.................................................................................................. 15-185
Interface Mode Configuration ............................................................................... 15-192
Frame Control Blocks........................................................................................ 15-161
Transmit Path Off-Load and Tx PTP Packet Parsing ........................................ 15-161
Receive Path Off-Load ...................................................................................... 15-163
Receive Parser ................................................................................................... 15-165
Receive Queue Filer .......................................................................................... 15-167
Transmission Scheduling................................................................................... 15-173
Back Pressure Determination through Free Buffers .......................................... 15-175
Features.............................................................................................................. 15-178
Timer Logic Overview....................................................................................... 15-179
Timestamp Insertion on the Received Packets .................................................. 15-179
PTP Packet Parsing ............................................................................................ 15-180
Timestamp Insertion on Transmit Packets......................................................... 15-181
Tx PTP Packet Parsing....................................................................................... 15-183
Data Buffer Descriptors ..................................................................................... 15-185
Transmit Data Buffer Descriptors (TxBD) ........................................................ 15-186
Receive Buffer Descriptors (RxBD).................................................................. 15-190
MII Interface Mode............................................................................................ 15-193
RGMII Interface Mode ...................................................................................... 15-196
Software Use of Hardware-Initiated Back Pressure .......................................... 15-177
Filing Rules ................................................................................................... 15-168
Comparing Properties with Bit Masks........................................................... 15-169
Special-Case Rules ........................................................................................ 15-170
Filer Interrupt Events..................................................................................... 15-170
Setting Up the Receive Queue Filer Table .................................................... 15-171
Filer Example—802.1p Priority Filing.......................................................... 15-171
Filer Example—IP Diff-Serv Code Points Filing.......................................... 15-172
Filer Example—TCP and UDP Port Filing .................................................. 15-172
Priority-Based Queuing (PBQ)...................................................................... 15-174
Modified Weighted Round-Robin Queuing (MWRR) .................................. 15-174
Initialization................................................................................................... 15-177
Operation ....................................................................................................... 15-177
Timestamp Point ............................................................................................ 15-179
General Purpose Filer Rule............................................................................ 15-181
Interrupts........................................................................................................ 15-182
Error Condition.............................................................................................. 15-183
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