MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1096

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

I
17.4.1.3
Figure 17-8
terminate the previous transfer. The master uses this method to communicate with another slave or with
the same slave in a different mode (transmit/receive mode) without releasing the bus.
17.4.1.4
The master can terminate the transfer by generating a STOP condition to free the bus. A STOP condition
is defined as a low-to-high transition of the SDAn signal while SCLn is high. For more information, see
Figure
at which point the slave must release the bus. The STOP condition is initiated by a software write that
clears I2CnCR[MSTA].
As described in
condition followed by a calling address without generating a STOP condition for the previous transfer.
This is called a repeated START condition.
17.4.1.5
The following sections give details of how aspects of the protocol are implemented in the I
17.4.1.5.1
The different conditions of the I
17.4.1.5.2
The I
of the I
module. The SDAn output can change only at the midpoint of a low cycle of the SCLn, unless it is
performing a START, STOP, or repeated START condition. Otherwise, the SDAn output is held constant.
SDAn is negated when one or more of the following conditions are true:
17-12
2
C Interfaces
•
•
•
•
•
2
C module contains logic that controls the output to the serial data (SDA) and serial clock (SCL) lines
17-8. Note that a master can generate a STOP even if the slave has transmitted an acknowledge bit,
2
START conditions are detected when an SDAn fall occurs while SCLn is high.
STOP conditions are detected when an SDAn rise occurs while SCLn is high.
Data transfers in progress are canceled when a STOP condition is detected or if there is a slave address
mismatch. Cancellation of data transactions resets the clock module.
The bus is detected to be busy upon the detection of a START condition and idle upon the detection
of a STOP condition.
Master mode
— Data bit (transmit)
— ACK bit (receive)
— START condition
— STOP condition
— Repeated START condition
C. The SCLn output is pulled low as determined by the internal clock generated in the clock
shows a repeated START condition, which is generated without a STOP condition that can
Repeated START Condition
STOP Condition
Protocol Implementation Details
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Transaction Monitoring—Implementation Details
Control Transfer—Implementation Details
Section 17.4.1.3, “Repeated START Condition,”
2
C data transfers are monitored as follows (see
the master can generate a START
Figure
Freescale Semiconductor
17-8):
2
C module.