MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 740

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

1
2
3
4
Enhanced Three-Speed Ethernet Controllers
15.5.3
This section provides a detailed description of all the eTSEC registers. Because all of the eTSEC registers
are 32 bits wide, only 32-bit register accesses are supported.
15.5.3.1
This section describes general control and status registers used for both transmitting and receiving Ethernet
frames. All of the registers are 32 bits wide.
15.5.3.1.1
The controller ID register (TSEC_ID) is a read-only register. The TSEC_ID register is used to identify the
eTSEC block and revision.
15-22
0x2_5000–
0x2_4EAC TMR_ETTS2_L*—Timestamp of general purpose external trigger
0x2_4EA0 TMR_ETTS1_H*—Timestamp of general purpose external
0x2_4EA4 TMR_ETTS1_L*—Timestamp of general purpose external trigger
0x2_4EA8 TMR_ETTS2_H*—Timestamp of general purpose external
0x2_4EB0
0x2_4FFF
0x2_5FFF
Offset eTSEC1:0x2_4000; eTSEC2:0x2_5000
Reset 0
eTSEC1
Registers denoted * are new to the enhanced TSEC and not supported by PowerQUICC II Pro TSECs.
Key: R = read only, WO = write only, R/W = read and write, LH = latches high, SC = self-clearing.
Cleared on read.
eTSEC2 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_5000 to 0x2_5FFF.
Offset
W
–
R
0
0
trigger
trigger
Reserved
eTSEC2 REGISTERS
Memory-Mapped Register Descriptions
eTSEC General Control and Status Registers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
Controller ID Register (TSEC_ID)
0
0
0
0
TSEC_ID
4
1
Table 15-4. Module Memory Map (continued)
0
Name
0
Figure 15-2. TSEC_ID Register
1
1
0
0
Other eTSECs
1
0
15 16
0
0
0
TSEC_REV_MJ
0
Access
0
R/W
R/W
R/W
R/W
—
0
2
0
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0
Reset
23 24
1
—
0
Freescale Semiconductor
0
TSEC_REV_MN
0
15.5.3.10.14/15-121
Access: Read only
0
Section/Page
0
—
1
1
31
0