MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 238

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MPC8313CZQADDC

Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8313CZQADDC

Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4

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System Configuration
the software watchdog timer for a certain period of time (for example, because software is lost or trapped
in a loop with no controlled exit).
Figure 5-18
The software watchdog timer is enabled after reset to cause a hardware reset if it times out. The user has
the option of disabling the software watchdog if it is not needed. If used, the software watchdog timer
requires a special service sequence to be executed periodically. Without this periodic servicing, the
software watchdog timer times out and issues a reset or a non-maskable interrupt.
5.4.2
The WDT includes the following key features:
5.4.3
The WDT unit can operate in the following modes:
5-30
Based on 16-bit prescaler and 16-bit down-counter
Provides a selectable range for the time-out period
Provides ~12.8-sec maximum software time-out delay for 333-MHz input clock
Functional and programming compatibility with MPC8260 watchdog timer
WDT enable/disable mode:
If the software watchdog timer is not needed, the user can disable it with software after a system
reset. When the watchdog timer is disabled, the watchdog counter and prescaler counter are held
in a stopped state.
WDT output reset/interrupt mode:
Without software periodic servicing, the software watchdog timer times out and issues a reset or a
nonmaskable interrupt (mcp)
WDT prescaled/non-prescaled clock mode:
The WDT counter clock can be prescaled by programming the SWCRR[SWPR] bit, which
controls the divide-by-65,536 of the WDT counter.
WDT Features
WDT Modes of Operation
shows a high-level block diagram of the WDT.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 5-18. Software Watchdog Timer High-Level Block Diagram
System
clock
Register Interface
Watchdog
Software
Timer
or mcp
Reset
Freescale Semiconductor

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