MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1046

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.6.14 Interrupts
The EHCI host controller hardware provides interrupt capability based on a number of sources. There are
several general groups of interrupt sources:
All transaction-based sources are maskable through the host controller's Interrupt Enable register
(USBINTR). Additionally, individual transfer descriptors can be marked to generate an interrupt on
completion. This section describes each interrupt source and the processing that occurs in response to the
interrupt.
During normal operation, interrupts may be immediate or deferred until the next interrupt threshold occurs.
The interrupt threshold is a tunable parameter via the Interrupt Threshold Control field in the USBCMD
register. The value of this register controls when the host controller generates an interrupt on behalf of
normal transaction execution. When a transaction completes during an interrupt interval period, the
interrupt signaling the completion of the transfer will not occur until the interrupt threshold occurs. For
example, the default value is eight micro-frames. This means that the host controller will not generate
interrupts any more frequently than once every eight micro-frames.
Section 16.6.14.2.4, “Host System Error”
If an interrupt has been scheduled to be generated for the current interrupt threshold interval, the interrupt
is not signaled until after the status for the last complete transaction in the interval has been written back
to system memory. This may sometimes result in the interrupt not being signaled until the next interrupt
threshold.
Initial interrupt processing is the same, regardless of the reason for the interrupt. When an interrupt is
signaled by the hardware, CPU control is transferred to host controller's USB interrupt handler. The precise
mechanism to accomplish the transfer is OS specific. For this discussion it is just assumed that control is
received. When the interrupt handler receives control, its first action is to reads the USBSTS. It then
acknowledges the interrupt by clearing all of the interrupt status bits by writing ones to these bit positions.
The handler then determines whether the interrupt is due to schedule processing or some other event. After
acknowledging the interrupt, the handler (via an OS-specific mechanism), schedules a deferred procedure
call (DPC) which will execute later. The DPC routine processes the results of the schedule execution. The
precise mechanisms used are beyond the scope of this document.
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Set the Port Test Control field in the port under test PORTSC register to the value corresponding
to the desired test mode. If the selected test is Test_Force_Enable, then USBCMD[RS] must then
be transitioned back to one, in order to enable transmission of SOFs out of the port under test.
When the test is complete, system software must ensure the host controller is halted (HCH bit is a
one) then it terminates and exits test mode by setting USBCMD[RST].
Interrupts as a result of executing transactions from the schedule (success and error conditions),
Host controller events (Port change events, etc.), and
Host controller error events
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
details effects of a host system error.
Freescale Semiconductor