MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 616

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
13.3.3.14 GPL Base Address Register 0
The GPL base address register 0 is provided to allow access to local memory space. This register is closely
tied to PIBAR0 and PIWAR0 in the CSR memory space. A write to GPL base address register 0 also causes
a change in the base address bits that are not masked according to the IWS field of PIWAR0 in PIBAR0.
Note that this write operation will not change the bits that are masked by the IWS field. For read operation
these masked bits will always return zeros.
Figure 13-32
Table 13-34
13.3.3.15 GPL Base Address Registers 1–2
The general purpose local access base address registers are provided to allow access to local memory
space. These registers are closely tied to PIBARn and PIWARn in the CSR memory space. A write to a
GPL base address register also causes a change in the base address bits that are not masked according to
the IWS field of PIWARn in the corresponding PIBARn. Note that this write operation will not change the
bits that are masked by the IWS field. For read operations, these masked bits always return zeros.
Figure 13-33
13-34
Offset 0x14, 0x18
Reset
31–12
Bits
2–1
Bits
W
2–1
R
3
0
0
31
Table 13-33. PIMMR Base Address Configuration Register Field Descriptions (continued)
shows the bit settings of the GPL base address register 0.
shows the GPL base address register 0 fields.
shows the GPL base address register 1–2 fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
Name
PRE
MSI
BA
MSI
T
T
Table 13-34. GPL Base Address Register 0 Field Descriptions
Base address. Defines the base address for the inbound window. Bits 11–4 are hard-wired to 0 since
the minimum window size is 4 Kbytes.
Prefetchable. This bit is read-only and contains the value of the PF bit in PIWAR0.
Type. Hard-wired to 00.
Memory space indicator. Hard-wired to 0
Type. Hard-wired to 00.
Memory space indicator. Hard-wired to 0
Figure 13-32. GPL Base Address Register 0
BA
All zeros
Description
Description
12 11
—
4
Freescale Semiconductor
PRE
3
Access: Read/Write
2
T
1
MSI
0