MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1102

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

I
Byte enables should be asserted for any byte that will be written, and they should be asserted contiguously,
creating a 1, 2, or 4 byte write to a register. The boot sequencer assumes that a big-endian address is stored
in the EEPROM. In addition, byte enable bit 0 (bit 1 of the byte) corresponds to the most-significant byte
of data (data[0:7]), and byte enable bit 3 (bit 4 of the byte) corresponds to the least-significant byte of data
(data[24:31]).
By asserting ACS, an alternate configuration space address is prepended to the write request from the boot
sequencer according to the value in the ALTCBAR register. This will allow for external memories to be
configured. Otherwise, IMMRBAR is prepended to the EEPROM address.
If the CONT bit is cleared, the first 3 bytes, including ACS, the byte enables, and the address, should be
cleared 0. Also, the data contains the final CRC. A CRC-32 algorithm is used to check the integrity of the
data. The following polynomial is used:
The CRC should cover all bytes stored in the EEPROM before the CRC. This includes the preamble, all
register preloads, and the first 3 bytes of the last 7-byte preload (which should be all zeros).
17-18
2
C Interfaces
•
•
A preamble should be the first 3 bytes programmed into the EEPROM. It should have a value of
0xAA55AA. The I
Following the preamble, there should be a series of configuration registers (known as register
preloads). Each configuration register should be programmed according to a particular format, as
shown in
— The first byte holds alternate configuration space (ACS), byte enables, and continue (CONT)
— The 2 least-significant bits of the address are derived from the byte enables. address offset.
— The most significant 16 bits (assuming 36-bit addressing) of the address are prepended from
— After the first 3 bytes, 4 bytes of data should hold the desired value of the configuration register,
attributes.
Therefore, the address offset programmed into the EEPROM preload should be a word offset.
either IMMRRBAR or alternate configuration space.
regardless of the size of transaction.
1 + x
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
Figure 17-10. EEPROM Data Format for One Register Preload Command
Figure
+ x
2
+ x
17-10.
ACS
0
2
4
C checks to ensure that this preamble is correctly detected before proceeding.
+ x
5
+ x
1
7
+ x
2
BYTE_EN
8
+ x
10
ADDR[14:21]
ADDR[12:29]
DATA[16:23]
DATA[24:31]
DATA[8:15]
3
DATA[0:7]
+ x
11
+ x
4
12
+ x
CONT
5
16
+ x
22
ADDR[12:13]
6
+ x
23
+ x
7
26
+ x
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