MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 197

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is
loaded at power-on reset or by one of the hard-coded reset options. See
The DDR SDRAM memory controller will operate with a frequency equal to twice the frequency of
csb_clk. Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR
clock divider (÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However,
the data rate is the same frequency as ddr_clk.
The local bus memory controller will operate with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock output (LCLK[0:1]). The LBC clock divider ratio is controlled by
LCCR[CLKDIV]. See
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
frequency. Refer to
4.4.4
If the on-chip USB PHY is utilized, the reference input can be provided externally using a separate clock
source, either a crystal or an external oscillator. The PHY supplies the clock to the USB DR controller in
UTMI mode (when the on-chip PHY is used). Synchronization between the PHY clock domain and the
CSB clock domain occurs in the USB controller.
An option is provided to supply the USB reference clock from the SYS_CLK_IN or SYS_CR_CLK_IN
inputs. This allows for a single crystal or clock input to supply both system and USB references. The USB
reference clock can be provided with a divide by 1 or 2 from these inputs (see
Freescale Semiconductor
USB Clocking
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The clock ratios of these units must be set before they are accessed.
eTSEC1 and eTSEC2 share the same clock control, and therefore the same
clock ratio. They can be independently switched off.
A portion of the eTSECn and USB DR controller run at the line rate on a
clock provided by the SGMII and USB PHY blocks, respectively.
Synchronization between the line rate clock and the csb_clk is provided in
these controllers.
eTSEC1 and eTSEC2
Security core, I
USB DR
PCI and DMA complex
Section 4.5.2.3, “System Clock Control Register (SCCR).”
Section 10.1.3.1, “eLBC Bus Clock and Clock Ratios,”
Unit
2
C1
Table 4-26. Configurable Clock Units
Default Frequency
Table 4-26
csb_clk
csb_clk
csb_clk
csb_clk
NOTE
NOTE
specifies which units have a configurable clock
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk /2, csb_clk /3
Off, csb_clk, csb_clk /2, csb_clk /3
Off, csb_clk
Section 4.3, “Reset Configuration.”
Options
Figure
Reset, Clocking, and Initialization
for more information.
4-7). When using the
4-31