MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1106

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

I
During slave-mode address cycles (I2CnSR[MAAS] is set), I2CnSR[SRW] should be read to determine
the direction of the subsequent transfer and I2CnCR[MTX] should be programmed accordingly. For
slave-mode data cycles (MAAS is cleared), I2CnSR[SRW] is not valid and I2CnCR[MTX] must be read
to determine the direction of the current transfer (see
17.5.5
A data transfer ends with a STOP condition generated by the master device. A master transmitter can
generate a STOP condition after all the data has been transmitted.
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data (by setting the transmit acknowledge bit (I2CnCR[TXAK])) before
reading the next-to-last byte of data. At this time, the next-to-last byte of data has been transferred on the
I
Before the interrupt service routine reads the last byte of data, a STOP condition must first be generated.
17.5.6
At the end of a data transfer, if the master still wants to communicate on the bus, it can generate another
START condition followed by another slave address without first generating a STOP condition. This is
accomplished by setting I2CnCR[RSTA].
17.5.7
It is sometimes necessary to force the I
SCLn (even though SDAn may already be driven, which indicates that the bus is busy). This can occur
when a system reset does not cause all I
I
procedure can be used to force this I
finish its transaction:
17.5.8
In the slave interrupt service routine, the module addressed as a slave should be tested to check if a calling
of its own address has been received. If I2CnSR[MAAS] is set, software should set the transmit/receive
mode select bit (I2CnCR[MTX]) according to the R/W command bit (I2CnSR[SRW]). Writing to I2CnCR
clears MAAS automatically. MAAS is read as set only in the interrupt handler at the end of that address
cycle where an address match occurred; interrupts resulting from subsequent data transfers clear MAAS.
A data transfer can then be initiated by writing to I2CnDR for slave transmits or dummy reading from
I2CnDR in slave-receive mode. The slave negates SCLn between byte transfers. SCLn is released when
I2CnDR is accessed in the required mode.
17-22
2
2
2
C Interfaces
C interface, so the last byte does not receive the data acknowledge (because I2CnCR[TXAK] is set).
C device while this I
1. Disable the I
2. Enable the I
3. Read I2CnDR.
4. Return the I
Generation of STOP
Generation of Repeated START
Generation of SCL n When SDA n is Negated
Slave Mode Interrupt Service Routine
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
2
2
C module to slave mode by setting I2CnCR to 0x80.
C module by setting I2CnCR to 0xA0.
C module and set the master bit by setting I2CnCR to 0x20.
2
C module is coming out of reset and will stay low indefinitely. The following
2
C module to generate SCLn so that the device driving SDAn can
2
2
C module to become the I
C devices to be reset. Thus, SDAn can be negated low by another
Figure
17-11).
2
C bus master out of reset and drive
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