MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 458

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.3.1.1
The base registers (BRn), shown in
memory bank. The memory controller uses this information to compare the address bus value with the
current address accessed. Each register (bank) includes a memory attribute and selects the machine for
memory operation handling. Note that after system reset, BR0[V] is set, BR1[V]–BR3[V] are cleared, and
the value of BR0[PS] reflects the initial port size configured by the boot ROM location field of the reset
configuration word.
Table 10-4
10-10
1
Offset BR0: 0x0_5000
17–18
19–20
21–22
Reset 0
0–16
Bits
BR0 has its valid bit (V) set for RCWH[ROMLOC] = LBC. Thus bank 0 is valid with the port size (PS) configured from
RCWH[ROMLOC] as loaded during reset. M = 0 for MSEL of GPCM, 1 for MSEL of FCM at boot. All other base registers
have all bits cleared to zero during reset.
23
W
R
BR1: 0x0_5008
BR2: 0x0_5010
BR3: 0x0_5018
0
DECC Specifies the method for data error checking.
Name
WP
BA
PS
—
0
describes BR
Base Registers (BR0–BR3)
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Base address. The upper 17 bits of each base register are compared to the address on the address bus to
determine if the bus master is accessing a memory bank controlled by the memory controller. Used with the
address mask bits OR n [AM].
Reserved
Port size. Specifies the port size of this memory region. For BR0, PS is configured from the field in reset
configuration word as loaded during reset. For all other banks the value is reset to 00 (port size not defined).
00 Reserved
01 8-bit
10 16-bit (not supported for FCM)
11 Reserved
00 Data error checking disabled. No ECC generation for FCM.
01 ECC checking is enabled, but ECC generation is disabled, for FCM on full-page transfers.
10 ECC checking and generation are enabled for FCM on full-page transfers.
11 Reserved
Write protect.
0 Read and write accesses are allowed.
1 Only read accesses are allowed. The memory controller does not assert LCS n on write cycles to this
0
memory bank. LTESR[WP] is set (if WP is set) if a write to this memory bank is attempted, and a local bus
error interrupt is generated (if enabled), terminating the cycle.
0
0
n
0
fields.
0
BA
0
0
Table 10-4. BR
Figure
Figure 10-2. Base Registers (BR
0
0 0
10-2, contain the base address and address types for each
0
n
0
Field Descriptions
0
Description
16 17 18 19 20 21 22
0
0
—
0 P S
PS
n
)
DECC WP
0
0
23
0
24
0
MSEL
Freescale Semiconductor
0 M 0
26 27 28 29 30 31
Access: Read/Write
— ATOM — V
0
0
1 V
1