MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 687

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.4.3.6
The AESU interrupt status register (AESUISR), shown in
if those errors are not masked, through the AESU interrupt control register (AESUICR).
Freescale Semiconductor
59–60
Bits
58
61
62
63
Reset
Field
Addr
R/W
Name
HALT
ICR
RD
IE
ID
0
AESU Interrupt Status Register (AESUISR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Halt. Indicates that the AESU has halted due to an error.
0 AESU not halted
1 AESU halted
Note: Because the error causing the AESU to stop operating may be masked before reaching the interrupt
Integrity check result
00 No integrity check was performed.
01 The integrity check passed.
10 The integrity check failed.
11 Reserved
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 AESU is not signaling error
1 AESU is signaling error
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 AESU is not signaling done
1 AESU is signaling done
Reset done. This status bit, when high, indicates that AESU has completed its reset sequence, as reflected
in the signal sampled by the channel.
0 Reset in progress
1 Reset done
Note: Reset done resets to 0, but has typically switched to 1 by the time a user checks the register, indicating
—
status register, the AESU interrupt status register (AESUISR) is used to provide a second source of
information regarding errors preventing normal operation.
the EU is ready for operation.
Figure 14-31. AESU Interrupt Status Register (AESUISR)
Table 14-28. AESUSR Field Descriptions (continued)
48
ICE
49
(Section 14.6.4.3, “Interrupt Status Register
(Section 14.6.4.3, “Interrupt Status Register
—
50
IE
51
ERE CE KSE DSE ME AE OFE IFE IFU IFO OFU —
52
AESU 0x3_4030
53
Description
R
0
54
Figure
55
14-31, tracks the state of possible errors,
56
57
(ISR)”).
(ISR)”).
58
59
Security Engine (SEC) 2.2
60
61
62
63
14-45