MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 563

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x030
12.3
The following sections describe the DMA/messaging unit configuration, control, and status registers.
12.3.1
OMISR contains the interrupt status of the doorbell and outbound message registers. A PCI device
acknowledges the outbound message interrupt by writing a 1 to the appropriate status bit: OMISR[OM1I]
or OMISR[OM0I]. Setting one of these bits clears both the interrupt and the corresponding status bit. The
local processor provokes an outbound message interrupt by writing to either of the two outbound message
registers: OMR0 or OMR1. OMISR can be accessed from the CSB or the PCI bus, but it is normally
accessed only from the PCI bus.
Reset
Freescale Semiconductor
0x0_82B0–
0x0_82A0
0x0_82A4
0x0_82A8
0x0_82FF
0x0_8218
0x0_8220
0x0_8224
0x0_8280
0x0_8284
0x0_8288
0x0_8290
0x0_8298
W
R
Offset
31
Register Descriptions
Outbound Message Interrupt Status Register (OMISR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
DMADAR2—DMA 2 destination address register
DMABCR2—DMA 2 byte count register
DMANDAR2—DMA 2 next descriptor address register
DMAMR3—DMA 3 mode register
DMASR3—DMA 3 status register
DMACDAR3—DMA 3 current descriptor address register
DMASAR3—DMA 3 source address register
DMADAR3—DMA 3 destination address register
DMABCR3—DMA 3 byte count register
DMANDAR3—DMA 3 next descriptor address register
DMAGSR—DMA general status register
Reserved
The registers described in this section use little-endian byte ordering.
Software running on the local processor in big-endian mode must byte-swap
the data. No byte swapping occurs when the registers are accessed from the
PCI bus.
Figure 12-2. Outbound Message Interrupt Status Register (OMISR)
Table 12-1. Module Memory Map (continued)
Figure 12-2
Register
—
shows the OMISR fields.
NOTE
All zeros
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
4
—
ODI
3
DMA/Messaging Unit
—
12.3.8.5/12-13
12.3.8.6/12-14
12.3.8.7/12-14
12.3.8.2/12-11
12.3.8.3/12-12
12.3.8.4/12-13
12.3.8.5/12-13
12.3.8.6/12-14
12.3.8.7/12-14
12.3.8.8/12-15
2
Section/Page
12.3.8.1/12-9
Access: Mixed
OM1I OM0I
w1c
—
1
w1c
12-3
0