MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1078

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.9.1.4
The same data structures used for FS/LS transactions though a HS hub are also used for transactions
through the Root Hub. Here it is demonstrated how the Hub Address and Endpoint Speed fields should be
set for directly attached FS/LS devices and hubs:
16.9.1.5
The operational models are well defined for the behavior of the transaction translator (see Universal Serial
Bus Revision 2.0 Specification) and for the EHCI controller moving packets between system memory and
a USB-HS hub. Since the embedded transaction translator exists within the DR module there is no physical
bus between EHCI host controller driver and the USB FS/LS bus. These sections will briefly discuss the
operational model for how the EHCI and transaction translator operational models are combined without
the physical bus between. The following sections assume the reader is familiar with both the EHCI and
USB 2.0 transaction translator operational models.
16.9.1.5.1
The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline between
the Host (H) and the Bus (B). The embedded transaction translator shall use the same pipeline algorithms
specified in the Universal Serial Bus Revision 2.0 Specification for a Hub-based transaction translator.
All periodic transfers always begin at B-frame 0 (after SOF) and continue until the stored periodic transfers
are complete. As an example of the microframe pipeline implemented in the embedded transaction
translator, all periodic transfers that are tagged in EHCI to execute in H-frame 0 will be ready to execute
on the bus in B-frame 0.
It is important to note that when programming the S-mask and C-masks in the EHCI data structures to
schedule periodic transfers for the embedded transaction translator, the EHCI host controller driver must
16-150
1. QH (for direct attach FS/LS)—Async. (Bulk/Control Endpoints) Periodic (Interrupt)
•
•
•
2. siTD (for direct attach FS)—Periodic (ISO Endpoint)
•
Hub Address = 0
Transactions to direct attached device/hub.
— QH.EPS = Port Speed
Transactions to a device downstream from direct attached FS hub.
— QH.EPS = Downstream Device Speed
Maximum Packet Size must be less than or equal 64 or undefined behavior may result.
All FS ISO transactions:
— Hub Address = 0
— siTD.EPS = 00 (full speed)
Maximum Packet Size must less than or equal to 1023 or undefined behavior may result.
Data Structures
Operational Model
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
When QH.EPS = 01 (LS) and PORTSC[PSPD] = 00 (FS), a LS-pre-pid will
be sent before the transmitting LS traffic.
Microframe Pipeline
NOTE
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