MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 677

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.4.2.7
The MDEU interrupt status register (MDEUISR), shown in
errors, if those errors are not masked, through the MDEU interrupt control register (MDEUICR).
Table 14-23
Freescale Semiconductor
0–48
Bits
Bits
62
63
49
50
51
52
Reset
Field
Addr
R/W
Name
Name
ERE
ICE
RD
—
—
IE
ID
describes the MDEUISR fields.
MDEU Interrupt Status Register (MDEUISR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 MDEU is not signaling done
1 MDEU is signaling done
Reset done. This status bit, when high, indicates that MDEU has completed its reset sequence, as reflected
in the signal sampled by the channel.
0 Reset in progress
1 Reset done
Note: Reset done resets to 0, but has typically switched to 1 by the time a user checks the register, indicating
Reserved
Integrity check error
0 No error detected
1 Integrity check error detected. An ICV check was performed and the supplied ICV did not match the one
Reserved
Internal error. Indicates the MDEU has been locked up and requires a reset before use.
0 No internal error detected
1 Internal error detected
Note: This bit will be asserted any time an enabled error condition occurs and can only be cleared by
Early read error. The MDEU context was read before the MDEU completed the hashing operation.
0 No error detected
1 Early read error
computed by the MDEU.
the EU is ready for operation.
resetting the MDEU.
Figure 14-21. MDEU Interrupt Status Register (MDEUISR)
—
Table 14-22. MDEUSR Field Descriptions (continued)
Table 14-23. MDEUISR Field Descriptions
(Section 14.6.4.3, “Interrupt Status Register
ICE
49
—
50
MDEU 0x3_6030
51
IE ERE CE KSE DSE ME AE
64’h1000
Description
Description
52
R
Figure
53
54
14-21, tracks the state of possible
55
(ISR)”).
56
57
58
—
Security Engine (SEC) 2.2
60
IFO
61
62 63
—
14-35