MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1162

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
4.5.2, 4-38
Chapter 5, Throughout Added that LBLAWAR0[EN], PCILAWAR[EN], and DDRLAWAR[EN] are
5.3.2.3.1, 5-18
5.3.2.4, 5-18
5.3.2.4, 5-19
5.3.2.4, 5-19
5.3.2.4, 5-20
5.3.2.5, 5-21
5.3.2.6, 5-23
5.3.2.6, 5-24
A-4
Offset 0x00110
Reset
Reset
12–15
16–17 TSEC1588 00 Selects 1588 pins muxed with eTSEC1 (default)
0
1
2
W
W
R
R
BUFGTX
BUFGTX125 0 A signal is supplied from an external PHY or oscillator to TSEC1_GTX_CLK125 has the same
BUFMDIO
125
16
0
—
TSEC1588
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
BUFMDIO —
Reserved. Should be cleared.
01 Selects 1588 pins muxed with LA[10:15] pads.
10 Selects 1588 pins muxed with UART2 + I2C1 pads.
11 Reserved
1 A 2.5-V signal is supplied to TSEC1_GTX_CLK125 from an external PHY or oscillator, and the LVdbb
0 A 3.3-V signal is supplied from external PHY to TSEC1_MDIO
1 A 2.5-V signal is supplied from external PHY to TSEC1_MDIO
Reserved. Should be cleared.
17
voltage level as the LVddb power supply. (Default)
power supply has a 3.3-V voltage level.
In Table 4-35, added a ‘Reset’ column.
dependent on RCWH[ROMLOC] and RCWH[RLEXT].
In Table 5-25, “REVID Coding,” updated REVID to 2.1
In Figure 5-13, replace with the following:
In Figure 5-13, “
updated to reflect dependency on CFG_RESET_SRC
In Table 5-26, changed bits 0 thru 2 to the following:
In Table 5-26, changed bits 12 thru 17 to the following:
In Figure 5-14, added bit numbers for bit 17, 18, 25, and 26 to the figure.
In Table 5-28, bit 7, changed the reset value to 1.
In Table 5-29, updated SICRH[7] and corresponding footer.
In Table 5-30, corrected bits 30 and 31 from LVDD1 and LVDD2 to lvddb and
lvdda, respectively.
18
TSECDP
PCIHPE
19
System Priority Configuration Register (SPCR),”
20
TSECBDP
—
21
All zeros
All zeros
TSECEP
22
PCIPR
23
7
OPT
24
8
TBEN
25
9
COREPR
10
26
Freescale Semiconductor
—
11
27
reset value
12
28
29
Read/Write
—
Access:
30
15
31