MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 219

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.2.4.6
The PCI local access window n attributes registers (PCILAWAR0–PCILAWAR1) are shown in
Table 5-13
5.2.4.6.1
The core may use a PCI peripheral device to fetch its boot vector. For this purpose an 8-Mbyte (2
local access window is defined by the PCILAWBAR0[SIZE] reset value, and PCILAWAR0 is enabled
according to the value set in the reset configuration word high ROMLOC and RLEXT fields.
Table 5-14
Freescale Semiconductor
RCWHR[RLEXT]/RCWHR
Offset 0x64
26–31
Reset
1–25
‘
‘
Bits
0
W
R
000, 011–111
0x6C
1
2
EN
[ROMLOC]
0
Name
The reset value of PCILAWAR0[EN] depends on RCWH[RLEXT] and RCWH[ROMLOC]. See
“PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value,”
The reset value of PCILAWAR0[SIZE] is always 0b010110, meaning an 8-Mbyte local access window. See
Section 5.2.4.6.1, “PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value,”
Figure 5-7. PCI Local Access Window n Attributes Registers (PCILAWAR0–PCILAWAR1)
SIZE
EN
—
001
1
defines the bit fields of PCILAWAR0–PCILAWAR1.
defines the reset value of PCILAWAR0[EN].
PCI Local Access Window n Attributes Registers
(PCILAWAR0–PCILAWAR1)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value
0 The PCI local access window n is disabled.
1 The PCI local access window n is enabled and other PCILAWAR n and PCILAWBAR n fields combine to
Reserved. Write has no effect, read returns 0.
Identifies the size of the window from the starting address. Window size is 2
000000–001010 Reserved. Window is undefined.
001011 4 Kbytes
001100 8 Kbytes
001101 16 Kbytes
. . . . . . . 2
011110 2 Gbytes
011111–111111 Reserved. Window is undefined.
identify an address range for this window.
(SIZE+1)
PCILAWR0[EN]
Reset Value
Table 5-13. PCILAWAR0–PCILAWAR1 Bit Settings
bytes
0
1
Table 5-14. PCILAWAR0[EN] Reset Value
e300c3 core boot not performed from a PCI device.
e300c3 core boot performed from a PCI device. PCI 8-Mbyte (2
access window is enabled.
—
All zeros
Description
for a detailed description.
1,2
Description
for a detailed description
(SIZE+1)
25 26
bytes.
Section 5.2.4.6.1,
Access: Read/Write
System Configuration
SIZE
Figure
(22+1)
(22+1)
) local
5-7.
5-11
31
)