MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 50

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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Receive Frame Length Error Counter Register Definition ................................................. 15-87
Receive Code Error Counter Register Definition ............................................................... 15-88
Receive Carrier Sense Error Counter Register Definition .................................................. 15-88
Receive Undersize Packet Counter Register Definition ..................................................... 15-89
Receive Oversize Packet Counter Register Definition ....................................................... 15-89
Receive Fragments Counter Register Definition ................................................................ 15-90
Receive Jabber Counter Register Definition....................................................................... 15-90
Receive Dropped Packet Counter Register Definition ....................................................... 15-91
Transmit Byte Counter Register Definition ........................................................................ 15-91
Transmit Packet Counter Register Definition ..................................................................... 15-92
Transmit Multicast Packet Counter Register Definition ..................................................... 15-92
Transmit Broadcast Packet Counter Register Definition .................................................... 15-93
Transmit Pause Control Frame Counter Register Definition .............................................. 15-93
Transmit Deferral Packet Counter Register Definition....................................................... 15-94
Transmit Excessive Deferral Packet Counter Register Definition...................................... 15-94
Transmit Single Collision Packet Counter Register Definition .......................................... 15-95
Transmit Multiple Collision Packet Counter Register Definition....................................... 15-95
Transmit Late Collision Packet Counter Register Definition ............................................. 15-96
Transmit Excessive Collision Packet Counter Register Definition .................................... 15-96
Transmit Total Collision Counter Register Definition ........................................................ 15-97
Transmit Drop Frame Counter Register Definition ............................................................ 15-97
Transmit Jabber Frame Counter Register Definition .......................................................... 15-98
Transmit FCS Error Counter Register Definition ............................................................... 15-98
Transmit Control Frame Counter Register Definition ........................................................ 15-99
Transmit Oversized Frame Counter Register Definition .................................................... 15-99
Transmit Undersize Frame Counter Register Definition .................................................. 15-100
Transmit Fragment Counter Register Definition .............................................................. 15-100
Carry Register 1 (CAR1) Register Definition................................................................... 15-101
Carry Register 2 (CAR2) Register Definition................................................................... 15-102
Carry Mask Register 1 (CAM1) Register Definition........................................................ 15-103
Carry Mask Register 2 (CAM2) Register Definition........................................................ 15-105
Receive Filer Rejected Packet Counter Register Definition ............................................. 15-106
IGADDRn Register Definition ......................................................................................... 15-107
GADDRn Register Definition........................................................................................... 15-107
ATTR Register Definition ................................................................................................. 15-108
RQPRM Register Definition ............................................................................................. 15-109
RFBPTR0–RFBPTR7 Register Definition........................................................................ 15-110
TMR_CTRL Register Definition .......................................................................................15-111
TMR_TEVENT Register Definition................................................................................. 15-113
TMR_PEVENT Register Definition................................................................................. 15-115
TMR_PEMASK Register Definition ................................................................................ 15-116
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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