MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 567

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

12.3.5.2
IDR is accessible from the PCI bus and the CSB in both host and agent modes.
fields.
Table 12-7
12.3.6
The IMISR contains the interrupt status of the doorbell and message register events. Writing a 1 to IM1I
clears the bit. The events are generated by the PCI masters.
Figure 12-8
Offset 0x080
Freescale Semiconductor
Reset
Offset: 0x068
Reset
Reset
30–0
Bits
31
W
R
W
W
R
R
31
IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9
IMC IDR30 IDR29 IDR28 IDR27 IDR26 IDR25 IDR24 IDR23 IDR22 IDR21 IDR20 IDR19 IDR18 IDR17 IDR16
31
15
Name
IDR n
IMC
describes the IDR registers.
Inbound Message Interrupt Status Register (IMISR)
shows the IMISR fields.
Inbound Doorbell Register (IDR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
30
14
Inbound machine check.
Write 1 from the PCI bus to set.
Write 1 from the CSB to clear.
Writing 0 has no effect.
Writing this bit from the PCI bus causes a machine check interrupt to be generated to the local processor.
Inbound doorbell n .
Write 1 from the PCI bus to set.
Write 1 from the CSB to clear.
Writing 0 has no effect.
Writing a bit in this register from the PCI bus causes an interrupt to be generated to the local processor.
29
13
Figure 12-8. Inbound Message Interrupt Status Register (IMISR)
28
12
Figure 12-7. Inbound Doorbell Register (IDR)
27
11
Table 12-7. IDR Field Descriptions
26
10
25
—
9
IDR8 IDR7 IDR6 IDR5 IDR4
24
All zeros
All zeros
8
All zeros
Descriptions
23
7
22
6
21
5
20
4
Figure 12-7
IDR3 IDR2 IDR1 IDR0
19
3
Access: User read/write
4
MCI IDI
DMA/Messaging Unit
Access: User Mixed
18
3
2
shows the IDR
2
17
1
—
1
16
12-7
IM1I
w1c
0
0