MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 416

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
9.4.1.9
The DDR SDRAM mode configuration register, shown in
DDR’s mode registers.
9-22
16–19
20–26
28–31
Bits
27
Offset 0x118
Reset
W
R
NUM_PR
0
D_INIT
Name
—
—
DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 9-10. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)
Table 9-13. DDR_SDRAM_CFG_2 Field Descriptions (continued)
one time. Note that if posted refreshes are used, then this field, along with
DDR_SDRAM_INTERVAL[REFINT], must be programmed such that the maximum t
cannot be violated. For example, some DDR1 SDRAMs are not able to use more than 3 posted
refreshes because the required refresh interval could then exceed the maximum constraint for t
0000 Reserved
0001 1 refresh is issued at a time
0010 2 refreshes is issued at a time
0011 3 refreshes is issued at a time
...
1000 8 refreshes is issued at a time
1001–1111 Reserved
Reserved, should be cleared.
bit before the memory controller is enabled, the controller automatically initializes DRAM after it is
enabled. This bit is automatically cleared by hardware once the initialization is completed. This data
initialization bit should only be set when the controller is idle.
0 There is not data initialization in progress, and no data initialization is scheduled
1 The memory controller initializes memory once it is enabled. This bit remains asserted until the
Reserved
Number of posted refreshes. This determines how many posted refreshes, if any, can be issued at
DRAM data initialization This bit is set by software, and it is cleared by hardware. If software sets this
initialization is complete. The value in DDR_DATA_INIT register is used to initialize memory.
ESDMODE
All zeros
15 16
Description
Figure
9-10, sets the values loaded into the
SDMODE
Freescale Semiconductor
Access: Read/Write
ras
specification
31
ras
.