MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 445

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
ACTTOPRE
ACTTOACT
ACTTORW
Parameter
WRTORD
ADD_LAT
REFREC
WR_LAT
CASLAT
WRREC
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 9-35. Programming Differences Between Memory Types (continued)
Activate to Precharge
Timing
Activate to Read/Write
Timing
CAS Latency
Refresh Recovery
Write Recovery
Activate A to Activate B
Write to Read Timing
Additive Latency
Write Latency
Description
DDR1
DDR2
DDR1
DDR2
DDR2
DDR2
DDR2
DDR1
DDR2
DDR2
DDR1
DDR2
DDR1
DDR2
DDR1
DDR1
DDR1
DDR1
Should be set, along with the Extended Activate to
Precharge Timing, according to the specifications
for the memory used (t
Should be set, along with the Extended Activate to
Precharge Timing, according to the specifications
for the memory used (t
the memory used (t
the memory used (t
Latency, to the desired CAS latency
Should be set, along with the Extended CAS
Latency, to the desired CAS latency
Recovery, to the specifications for the memory
used (t
Recovery, to the specifications for the memory
used (T
the memory used (t
the memory used (t
the memory used (t
the memory used (t
the memory used (t
the memory used (t
Should be set to 000
must be set to a value less than
TIMING_CFG_1[ACTTORW]
Should be set to 001
Should be set to CAS latency – 1 cycle. For
example, if the CAS latency if 5 cycles, then this
field should be set to 100 (4 cycles).
Should be set according to the specifications for
Should be set according to the specifications for
Should be set, along with the Extended CAS
Should be set, along with the Extended Refresh
Should be set, along with the Extended Refresh
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set to the desired additive latency. This
RFC
RFC
)
)
Differences
RCD
RCD
WR
WR
RRD
RRD
WTR
WTR
)
)
RAS
RAS
)
)
)
)
)
)
)
)
DDR Memory Controller
Section/Page
9.4.1.5/9-14
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9.4.1.5/9-14
9.4.1.5/9-14
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9.4.1.6/9-16
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