MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 935

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

1
The following sections provide details about the registers in the USB memory map.
16.3.1
The capability registers specify the software limits, restrictions, and capabilities of the host/device
controller implementation. Most of these registers are defined by the EHCI specification. Registers that
are not defined by the EHCI specification are noted in their descriptions.
Freescale Semiconductor
This register has separate functions for the host and device operation; the host function is listed first in the table.
0x2_31CA–
0x2_3504–
0x2_31D4
0x2_340C
0x2_3FFF
0x2_3400
0x2_3404
0x2_3408
0x2_3410
0x2_3500
Offset
Capability Registers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Memory may be viewed from either a big-endian or little-endian byte
ordering perspective depending on the processor configuration. In
big-endian mode, the most-significant byte of word 0 is located at address 0
and the least-significant byte of word 0 is located at address 3. In
little-endian mode, the least-significant byte of word 0 is located at address
0 and the most-significant byte of word 0 is located at address 3. Within
registers, bits are numbered within a word starting with bit 31 as the
most-significant bit. By convention USB registers use little-endian byte
ordering. In the USB DR module, these are the registers from offsets 0x00
to 0x1FF. The registers associated with the internal system interface (0x400
and above) use big-endian byte ordering.
Reserved
SNOOP1—Snoop 1
SNOOP2—Snoop 2
AGE_CNT_THRESH—Age count threshold
PRI_CTRL—Priority control
SI_CTRL—System interface control
CONTROL—Control
Reserved, should be cleared
Table 16-3. USB Interface Memory Map (continued)
Register
NOTE
Access
Mixed
R/W
R/W
R/W
R/W
R/W
—
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
Universal Serial Bus Interface
16.3.2.24/16-40
16.3.2.24/16-40
16.3.2.25/16-41
16.3.2.26/16-42
16.3.2.27/16-43
16.3.2.28/16-43
Section/Page
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