MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1173

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

13.3.3, 13-25
14.2, 14-9
14.6.4.5, 14-74
14.6.4.5, 14-74
Chapter 15, 15-1
15.4, 15-7
15.4.1, 15-8
15.5.2, 15-15
15.5.3.1.3, 15-24
15.5.3.1.3, 15-24
15.5.3.1.4, 15-28
Freescale Semiconductor
TSEC_1588_PP3
TSEC_1588_PP3
27
FGPI
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
a frame that matches a GPI rule sequence that is specified in the filer. It is synchronized with the setting of
RXF.
0 No filer generated interrupt has occurred.
1 The filer has accepted a frame via a matching rule that the RQFCR[GPI] bit set.
Filer generated general purpose interrupt on a set of filer rule match. This bit will be set upon reception of
1588—Pulse out 3
Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external output pin).
O
In Table 13-22, updated RID value from 10 to 21.
In Table 14-3, changed the ‘Section’ column to ‘Section/Page’ and added the page
numbers.
In the first paragraph, second sentence changed to read:
The value of ID is always 0x0000_0000_0002_00A0, indicating that this is the
first version of the SEC 2.2.
In Figure 14-45, changed the Reset value to: 0x0000_0000_0002_00A0.
Throughout the chapter remove text and references describing extraction of data
to allocate in the L2 cache. The MPC8313E does not support extraction to L2
cache.
In Table 15-1, for signal TSECn_RX_ER, in the Description column changed to:
RGMII, RTBI—Unused.
In Table 15-1, added signal TSEC_1588_PP3 as follows:
In Table 15-2, TSECn_CRS, State Meaning, changed reference from
TSECn_TX_CLK to TSECn_CRS.
In TEC_GTX-CLK125, Description column, added the following statement:
This input is not used in these modes:
In Table 15-2, added Signal TSEC_1588_PP3, as follows:
In Table 15-4, corrected the values for RQFCR and RQFPR as follows:
0xnnnn_nnnn
After item #3, added a fourth sub-bullet as follows:
— Special function interrupts are: MSRO, MMRD, and MMRW
In Figure 15-4, changed bit 27 to FGPI.
In Table 15-7, add the following for bit 27, FGPI:
In Figure 15-5, bit 26, changed to FGPIEN.
In Table 15-8, changed bits 25–27 to the following:
1588 pulse out 3. Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external
output pin)
• RMII
• SGMII
• MII
Revision History
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