MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 455

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
LSRCID[0:4]
LAD[0:15]
LCLK[0:1]
LA[0:25]
LBCTL
LDVAL
Signal
Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions (continued)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
I/O Multiplexed address/data bus. For a port size of 16 bits, LAD[0:7] connect to the most-significant byte lane
O
O
O
O
O
Data buffer control. The memory controller activates LBCTL for the local bus when a GPCM-, UPM-, or
FCM-controlled bank is accessed. Buffer control is disabled by setting OR n [BCTLD].
Nonmultiplexed address bus. All bits driven on LA[0:25] are defined for 8-bit port sizes. For 16-bit port
sizes LA[25] is a don’t care.
(at address offset 0), while LAD[8:15] connect to the least-significant byte lane (at address offset 1). For
a port size of 8 bits, only LAD[0:7] are connected to the external RAM.
Local bus clocks
Local bus data valid (eLBC debug mode only)
Local bus source ID (eLBC debug mode only). In debug mode, all LSRCID[0:4] pins are driven high
unless LSRCID[0:4] is driving a debug source ID for identifying the internal system device controlling the
eLBC.
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—During assertion of LALE, LAD are driven with the RAM address for the
Timing Assertion/Negation—Valid only while the eLBC is in system debug mode. In debug mode,
State
State
State
State
State
State
Asserted/Negated—The LBCTL pin normally functions as a write/read control for a bus
Asserted/Negated—LA is the address bus used to transmit addresses to external RAM
Asserted/Negated—LAD is the shared 16-bit address/data bus through which external RAM
Asserted/Negated—LCLK[0:1] drive an identical bus clock signal for distributed loads.
Asserted/Negated—For a read, LDVAL asserts for one bus cycle in the cycle immediately
Asserted/Negated—Remain high until the last bus cycle of the assertion of LALE, in which
transceiver connected to the LAD lines. Note that an external data buffer must not drive
the LAD lines in conflict with the eLBC when LBCTL is high, because LBCTL remains
high after reset and during address phases.
devices. Refer to
multiplexing.
devices transfer data and receive addresses.
access to follow. External logic should propagate the address on LAD while LALE is
asserted, and latch the address upon negation of LALE. After LALE is negated, LAD are
either driven by write data or are made high-impedance by the eLBC in order to sample
read data driven by an external device. Following the last data transfer of a write access,
LAD are again taken into a high-impedance state.
preceding the sampling of read data on LAD. For a write, LDVAL asserts for one bus cycle
during the final cycle for which the current write data on LAD is valid. During burst
transfers, LDVAL asserts for each data beat.
LDVAL asserts when the eLBC generates a data transfer acknowledge.
case the source ID of the address is indicated, or until LDVAL is asserted, in which case
the source ID relating to the data transfer is indicated. In case of address debug,
LSRCID[0:4] is valid only when the address on LAD consists of all physical address
bits—with optional padding—for reconstructing the system address presented to the
eLBC.
Section 10.5, “Initialization/Application Information,”
Description
Enhanced Local Bus Controller
for address signal
10-7