MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 978

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.5.3.1
The first DWord of an iTD is a pointer to the next schedule data structure.
16-50
1
2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
31–5
Bits
4–3
2–1
Host controller read/write; all others read-only.
These fields may be modified by the host controller if the I/O field indicates an OUT.
Status
Status
Status
Status
Status
Status
Status
Status
0
1
1
1
1
1
1
1
1
Link Pointer Correspond to memory address signals [31:5], respectively. This field points to another isochronous
Name
Typ
—
T
Next Link Pointer
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
transaction descriptor (iTD/siTD) or queue head (QH).
Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
Software should initialize this field to zero.
Indicates to the host controller whether the item referenced is an iTD, siTD or a QH. This allows the host
controller to perform the proper type of processing on the item after it is fetched. Value encodings are:
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (frame span traversal node)
Terminate
1 Link Pointer field is not valid.
0 Link Pointer field is valid.
Transaction 0 Length
Transaction 1 Length
Transaction 2 Length
Transaction 3 Length
Transaction 4 Length
Transaction 5 Length
Transaction 6 Length
Transaction 7 Length
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Buffer Pointer (Page 5)
Buffer Pointer (Page 6)
Figure 16-38. Isochronous Transaction Descriptor (iTD)
Table 16-40. Next Schedule Element Pointer
Next Link Pointer
1
1
1
1
1
1
1
1
ioc
ioc
ioc
ioc
ioc
ioc
ioc
ioc
15
14 13 12
PG
PG
PG
PG
PG
PG
PG
PG
Description
2
2
2
2
2
2
2
2
I/O
11
EndPt
10
9
Transaction 0 Offset
Transaction 1 Offset
Transaction 2 Offset
Transaction 3 Offset
Transaction 4 Offset
Transaction 5 Offset
Transaction 6 Offset
Transaction 7 Offset
8
Maximum Packet Size
Reserved
R
7
Reserved
Reserved
Reserved
Reserved
6
Device Address
5
Freescale Semiconductor
4
00
3
2
2
2
2
2
2
2
2
2
Typ
1
Mult
T 0x00
0
0x0C
0x1C
0x2C
0x3C
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
offset