MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 415

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

9.4.1.8
The DDR SDRAM control configuration register 2, shown in
configuration for the DDR controller.
Table 9-13
Freescale Semiconductor
11–15
9–10
Offset 0x114
Reset
Reset
Bits
4–5
6–8
0
1
2
3
W
W
R
R
FRC_SR
DLL_RST_DIS
DQS_CFG
ODT_CFG
16
0
FRC_SR
describes the DDR_SDRAM_CFG_2 fields.
Name
Figure 9-9. DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)
—
—
—
—
DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
1
NUM_PR
DLL_RST_DIS — DQS_CFG
Force self refresh
0 DDR controller operates in normal mode.
1 DDR controller enters self-refresh mode.
Reserved. Should be cleared.
0 DDR controller issues a DLL reset to the DRAMs when exiting self refresh.
1 DDR controller does not issue a DLL reset to the DRAMs when exiting self refresh.
Reserved
DQS configuration
00 Only true DQS signals are used.
01 Reserved
10 Reserved
11 Reserved
Reserved
“DDR Control Driver Register (DDRCDR),”
(DDR2-specific, must be cleared for DDR1)
00 Never assert ODT to internal IOs
01 Assert ODT to internal IOs only during writes to DRAM
10 Assert ODT to internal IOs only during reads to DRAM
11 Always keep ODT asserted to internal IOs
Reserved.
DLL reset disable. The DDR controller typically issues a DLL reset to the DRAMs when exiting self
ODT configuration. This field defines how ODT is driven to the on-chip IOs. See
refresh. However, this function may be disabled by setting this bit during initialization.
Table 9-13. DDR_SDRAM_CFG_2 Field Descriptions
2
19
3
20
4
5
6
All zeros
All zeros
—
8
—
which defines the termination value that is used.
Description
Figure
ODT_CFG
9
9-9, provides more control
10
26
D_INIT
11
27
DDR Memory Controller
28
Access: Read/Write
Section 5.4.4.12,
—
—
9-21
15
31