MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 967

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.3.2.23 Endpoint Control Register n (ENDPTCTRL n )—Non-EHCI
These registers are not defined in the EHCI specification. There is an ENDPTCTRLn register of each
endpoint in a device.
Freescale Semiconductor
31–24
19–18
Offset 0x2_31C4 (ENDPTCTRL1), 0x2_31C8 (ENDPTCTRL2),
Reset
15–8
Bits
23
22
21
20
17
16
7
W
R
31
Name
TXR
TXD
RXE
TXE
TXT
TXS
TXI
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared
TX endpoint enable
0 Disabled
1 Enabled
TX data toggle reset. Whenever a configuration event is received for this endpoint, software must write a one to
this bit in order to synchronize the data PID’s between the Host and device.
TX data toggle inhibit. Used only for test and should always be written as zero. Writing a one to this bit will cause
this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet.
0 PID sequencing enabled
1 PID sequencing disabled
Reserved, should be cleared
TX endpoint type
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
TX endpoint data source. This bit should always be written as 0, which selects the dual port memory/DMA
engine as the source.
TX endpoint stall. This bit will be set automatically upon receipt of a SETUP request if this endpoint is not
configured as a control endpoint. It will be cleared automatically upon receipt of a SETUP request if this endpoint
is configured as a control endpoint.
Software can write a one to this bit to force the endpoint to return a STALL handshake to the host. It will continue
to returning STALL until this bit is either cleared by software or automatically cleared as above.
0 Endpoint OK
1 Endpoint stalled
Reserved, should be cleared
RX endpoint enable
0 Disabled
1 Enabled
—
24
TXE TXR TXI — TXT TXD TXS
Table 16-32. ENDPTCTRL n Register Field Descriptions
23
Figure 16-29. Endpoint Control 1 to 5 (ENDPTCTRL n )
22
21
20 19 18
17
All zeros
16
Description
15
—
8
RXE RXR RXI — RXT RXD RXS
7
6
Universal Serial Bus Interface
5
Access: Read/Write
4
3
2
1
16-39
0