MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 961

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
Bits
7–5
19
18
17
16
15
14
13
12
11
10
9
8
4
3
2
1
0
BSVIS
ASVIS
AVVIS
Name
1msT
DPS
BSE
BSV
ASV
AVV
IDIS
DP
VC
VD
OT
—
ID
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
B session valid interrupt status. Set when VBus has either risen above or fallen below the B session valid
threshold (0.8 VDC).
Software must write a one to clear this bit.
A session valid interrupt status. Set when VBus has either risen above or fallen below the A session valid
threshold (0.8 VDC).
Software must write a one to clear this bit.
A VBus valid interrupt status. Set when VBus has either risen above or fallen below the VBus valid threshold
(4.4 VDC) on an A device.
Software must write a one to clear this bit.
USB ID interrupt status. Set when a change on the ID input has been detected.
Software must write a one to clear this bit.
Reserved, should be cleared.
Data bus pulsing status
1 Pulsing detected on port
0 No pulsing on port
1 millisecond timer toggle. This bit toggles once per millisecond.
B session end
1 VBus is below the B session end threshold.
0 VBus is above the B session end threshold.
B session valid
1 VBus is above the B session valid threshold.
0 VBus is below the B session valid threshold.
A session valid
1 VBus is above the A session valid threshold.
0 VBus is below the A session valid threshold.
A VBus valid
1 VBus is above the A VBus valid threshold.
0 VBus is below the A VBus valid threshold.
USB ID
1 B device
0 A device
Reserved, writes should preserve reset value.
Data pulsing
1 The pullup on DP is asserted for data pulsing during SRP.
0 The pullup on DP is not asserted.
OTG termination. This bit must be set when the OTG device is in device mode.
1 Enable pulldown on DM
0 Disable pulldown on DM
Reserved, should be cleared.
VBUS charge. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP.
VBUS discharge. Setting this bit causes VBus to discharge through a resistor.
Table 16-24. OTGSC Register Field Descriptions (continued)
Description
Universal Serial Bus Interface
16-33