MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1172

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
10.5.6, 10-100
10.5.7, 10-102
11.4.1, 11-3
12.2, 12-2
12.3.1, 12-3
12.3.2, 12-5
12.3.8.1, 12-11
13.3, 13-11
13.3.2.11, 13-23
13.3.2.11, 13-23
13.3.2.12, 13-24
A-14
11–10
PRC
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCI read command. This field indicates the type of PCI read command to use.
00 Reserved
01 PCI read line
10 PCI read multiple
11 Reserved
contention may arise on LGPL4. A possible case is that the next transaction from
eLBC may try to use that pin as an output and since the NAND Flash device might
already be driving it, contention will occur. In case OP5 and OP6 operations are
skipped, it may also happen that a new command is issued to the NAND Flash
device even when the device has not yet finished processing the previous request.
This may also result in unpredictable behavior.
Added the following text at the end of the section:
If a UPM device has OE, it should not be asserted in the same RAM word as the
TA signal. If OE and TA are both asserted in the same RAM word, then the eLBC
may not be able to sample the correct data during reads. Therefore, OE must be
asserted earlier than TA.
Deleted Sections, 10.5.7, 10.5.7.1, and 10.5.7.1.1. Deleted Table 10-48 and
Figures 10-80 through 10-82.
Table 11-2, in TA bit field description, added the following sentence: ‘The
translation address must be aligned based on the window’s size.’
Table 12-1, in 0x0_8030 row, Access column, changed to Mixed.
Figure 12-2, changed Access to ‘mixed’.
First paragraph, second sentence changed to read:
OMIMR can be read from the CSB or the PCI bus, but it can be written only from
the PCI bus.
In Table 12-10, changed bits 11-10 row to the following:
In Tables 13-4 and 13-5 added a ‘Reset’ column.
In the first paragraph, added the following:
Inbound and outbound windows for the same bus should not overlap. Therefore,
situations where an inbound window translation points back into an outbound
window, or where an outbound translation window points back into an inbound
window, are not allowed.
In Table 13-18, in the Description column for the TA bit added the following
sentence:
The specified address must be aligned to the window size, as defined by
PIWARn[IWS].
In Table 13-19, in the Description column for the BA bit added the following
sentence:
The specified address must be aligned to the window size, as defined by
PIWARn[IWS].
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