MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1151

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

20.3
The bypass, boundary-scan, and instruction JTAG registers and their associated scan chains are mandatory
for compliance with the IEEE 1149.1 specification.
Freescale Semiconductor
Signal
TRST
TDO
TMS
•
•
•
Bypass register. The bypass register is a single-stage register used to bypass the boundary-scan
latches of the device during board-level boundary-scan operations involving components other
than the device. The use of the bypass register reduces the total scan string size of the
boundary-scan test.
Boundary-scan registers. The JTAG interface provides a chain of registers dedicated to
boundary-scan operations. To be JTAG-compliant, these registers cannot be shared with any
functional registers of the device. The boundary-scan register chain includes registers controlling
the direction of the input/output drivers, in addition to the registers reflecting the signal value
received or driven.
The boundary-scan registers capture the input or output state of the device’s signals during a
Capture_DR TAP controller state. When a data scan is initiated following the Capture_DR state,
the sampled values are shifted out through the TDO output while new boundary-scan register
values are shifted in through the TDI input. At the end of the data scan operation, the
boundary-scan registers are updated with the new values during an update_DR TAP controller
state.
Instruction register. The 8-bit JTAG instruction register serves as an instruction and status register.
As TAP controller instructions are scanned in through the TDI input, the TAP controller status bits
are scanned out through the TDO output.
JTAG Registers and Scan Chains
I/O
O
I
I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
JTAG test data output.
JTAG test mode select.
JTAG test reset.
Meaning
Meaning
Meaning
Timing See IEEE 1149.1 specification for more details.
Timing See IEEE 1149.1 specification for more details.
Timing See IEEE 1149.1 specification for more details.
State
State
State
Table 20-2. JTAG Test—Detailed Signal Descriptions (continued)
Asserted/Negated—The contents of the selected internal instruction or data register are shifted out
Asserted/Negated—Decoded by the internal JTAG TAP controller to distinguish the primary
Asserted—Causes asynchronous initialization of the internal JTAG TAP controller. Must be asserted
Negated— Normal operation.
on this signal on the falling edge of TCK. Remains in a high-impedance state except when
scanning data.
operation of the test support circuitry. An unterminated input appears as a high signal level to
the test logic due to an internal pull-up resistor.
during power-on reset in order to properly initialize the JTAG TAP and for normal operation of
the device. An unterminated input appears as a high signal level to the test logic due to an
internal pull-up resistor.
Description
JTAG/Testing Support
20-3