MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 494

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.4.2.1
The basic GPCM read timing parameters that may be set by the ORn attributes are shown in
The read access cycle commences upon latching of the memory address (LALE negated), and concludes
when LBCTL returns high to turn the local bus around for a subsequent address phase. Read data is
captured by eLBC on the falling edge of TA. LOE and LCSn negate high simultaneously, in some cases
before the end of the read access to provide additional hold time for the external memory.
Table 10-32
varied.
10-46
Figure 10-33. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8)
lists the signal timing parameters for a GPCM read access as the option register attributes are
LBCTL
GPCM Read Signal Timing
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
LCLK
LCS n
LALE
LOE
LAD
TA
A
A[19:0]
Notes:
t
t
t
LCS n
LALE
RC
ARCS
AOE
LCLK
LOE
LAD
TA
= Read cycle time.
Address
= Address valid to output enable time.
= Address valid to read chip-select time.
Figure 10-34. GPCM General Read Timing Parameters
Address
ACS = 10
t
ARCS
t
AOE
ACS = 11
Latched Address
t
CSRP
Read Data
t
RC
t
t
CSRP
OEN
Latched Address
Read Data
= Output enable negated time.
= Read chip-select assertion period.
t
OEN
Freescale Semiconductor
Figure
10-34.