MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 786

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.5.2
The MACCFG2 register is written by the user.
register.
15-68
Offset eTSEC1:0x2_4504; eTSEC2:0x2_5504
Reset
Reset 0 1 1 1 0 0
24–25
Bits
26
27
28
29
30
31
W
W
R
R Preamble
16
0
Length
Sync’d Rx EN Receive enable synchronized to the receive stream. (Read-only)
Sync’d Tx EN Transmit enable synchronized to the transmit stream. (Read-only)
Rx_Flow
Tx_Flow
Rx_EN
Tx_EN
Name
19 20 21
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
MAC Configuration 2 Register (MACCFG2)
—
Reserved
Receive flow. This bit is cleared by default.
Must be 0 if MACCFG2[Full Duplex] = 0.
0 The receive MAC control ignores PAUSE flow control frames.
1 The receive MAC control detects and acts on PAUSE flow control frames.
Transmit flow. This bit is cleared by default.
Must be 0 if MACCFG2[Full Duplex] = 0.
0 The transmit MAC control may not send PAUSE flow control frames if requested by the system.
1 The transmit MAC control may send PAUSE flow control frames if requested by the system.
0 Frame reception is not enabled.
1 Frame reception is enabled.
Receive enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GRS] then
confirm subsequent occurrence of the graceful receive stop interrupt (IEVENT[GRSC] is set).
0 The MAC may not receive frames from the PHY.
1 The MAC may receive frames from the PHY.
0 Frame transmission is not enabled.
1 Frame transmission is enabled.
Transmit enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GTS] then
confirm subsequent occurrence of the graceful receive stop interrupt (IEVENT[GTSC] is set).
0 The MAC may not transmit frames from the system.
1 The MAC may transmit frames from the system.
22
Mode
0
I/F
Table 15-40. MACCFG1 Field Descriptions (continued)
23
0
PreAmRxEN PreAmTxEN
Figure 15-37. MACCFG2 Register Definition
24
0
25
0
Figure 15-37
All zeros
Frame
Huge
—
26
0
Description
describes the definition for the MACCFG2
Length
check
27
0
MPEN
28
0
PAD/CRC CRC EN
29
0
Freescale Semiconductor
Access: Read/Write
30
0
Duplex
Full
15
31
0