MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 463

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

1
10.3.1.2.3
Figure 10-4
Freescale Semiconductor
Offset OR0: 0x0_5004
Reset
Reset
Refer to
Bits
30
31
W
W
R
R
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
AM
16
0
Name
EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
Table 10-5
EAD
shows the bit fields for ORn when the corresponding BRn[MSEL] selects the FCM machine.
17
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Option Registers (OR
access from the current bank and the next access.
External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by
—
LCRR[EADC]).
for the OR0 reset value. All other option registers have all bits cleared.
18
TRLX
BCTLD
Table 10-7. OR
0
0
1
1
19
Figure 10-4. Option Registers (OR
20
—
EHTR
0
1
0
1
PGS CSCT CST
21
n
n
—
)—FCM Mode
The memory controller generates normal timing. No additional
cycles are inserted.
1 idle clock cycle is inserted.
4 idle clock cycles are inserted.
8 idle clock cycles are inserted.
GPCM Field Descriptions (continued)
22
23
All zeros
All zeros
AM
Description
CHT
24
1
n
25
) in FCM Mode
SCY
Meaning
27
RST
28
Enhanced Local Bus Controller
TRLX
29
Access: Read/Write
EHTR
30
10-15
—
15
31