MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 901

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure 15-142
15.6.6.5.2
When an error is encountered after a PTP packet has begun to be processed, the timestamp written to the
TxPAL is zero. Subsequent frames may be flushed by eTSEC. There will be no timestamp update to
TxPAL for the subsequent flushed frames.
15.6.6.6
Software instructs the Tx packet to be timestamped via setting bit 15 in the TxFCB to mark a PTP packet.
TxFCB[VLCTL] can be translated as the Tx PTP packet identification number. BD[TOE] must be set to
enable transmit PTP packet timestamping. TxFCB[PTP] bit takes precedence over TxFCB[VLN] bit. It
disables per packet VLAN tag insertion. On a PTP packet, a VLAN tag can be inserted from the DFVLAN
register. The TxFCB for the PTP packet is shown in
Freescale Semiconductor
Offset + 0
Offset + 2
Offset + 4
Offset + 6
TX BD Ring
Tx PTP Packet Parsing
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
depicts the buffer format requirements for timestamp insertion on transmit packets.
Error Condition
VLN
0
Data Buffer Length=8
Data Buffer Pointer
Data Buffer Length=M
Data Buffer Pointer
Figure 15-142. Buffer Format for Transmit timestamp Insertion
IP
1
IP6
2
Figure 15-143. Transmit Frame Control Block
TUP UDP CIP CTU NPH
3
TOE=1
L4OS
4
5
6
VLCTL/PTP_ID
Figure
7
PHCS
External Memory
15-143.
8
0 1
32B cache-lines
9
FCB
Enhanced Three-Speed Ethernet Controllers
8 Bytes
10
2
3
11
L3OS
...
12
7
13
TxPAL
TxPAL
TxFCB
TxPAL
FRAME
Unknown
Unknown
14
PTP
15
15-183