MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 965

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.3.2.21 Endpoint Complete Register (ENDPTCOMPLETE)—Non-EHCI
This register is not defined in the EHCI specification. This register is only used in device mode.
Freescale Semiconductor
Offset 0x2_31BC
Reset
31–19
18–16 ETCE Endpoint transmit complete event. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software
31–19
18–16 ETBR Endpoint transmit buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer.
15–3
Bits
15–3
2–0
Bits
2–0
W
R
31
Name
ERCE Endpoint receive complete event. Each bit indicates a received event (OUT/SETUP) occurred and software
ERBR Endpoint receive buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. This
Name
—
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared
should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit
is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear
the corresponding bit in this register. ETCE[2] (bit 18 of the register) corresponds to endpoint 2.
Reserved, should be cleared
should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is
set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear
the corresponding bit in this register. ERCE[2] corresponds to endpoint 2.
Reserved, should be cleared
This bit is set by the hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and
endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits
set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through
the ENDPTFLUSH register. ETBR[2] (bit 18 of the register) corresponds to endpoint 2.
Note that these bits will be momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
Reserved, should be cleared
bit is set by the hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and
endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits
set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through
the ENDPTFLUSH register. ERBR[2] corresponds to endpoint 2.
Note that these bits will be momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
Table 16-30. ENDPTCOMPLETE Register Field Descriptions
Table 16-29. ENDPTSTATUS Register Field Descriptions
—
Figure 16-27. Endpoint Complete (ENDPTCOMPLETE)
21
19 18
ETCE
w1c
All zeros
Description
16 15
Description
—
Universal Serial Bus Interface
Access: w1c
3
2
ERCE
w1c
16-37
0